Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > FPGAs/PLDs

Quartus II software version 8.1 rolls

Posted: 05 Nov 2008 ?? ?Print Version ?Bookmark and Share

Keywords:software Quartus II? ASIC? FPGA?

The folks at Altera have unveiled their Quartus II software version 8.1 for CPLD, FPGA, and HardCopy ASIC designs. Based on internal benchmarks, the folks at Altera claim high-density FPGA compile times three times faster than other FPGA-vendor supplied development software.

Faster design development
While next-generation FPGAs deliver a greater level of functionality, design teams continue to be constrained by limited development times. Quartus II software version 8.1 helps speed development times by automating traditionally time-consuming features.

The design partition planner, introduced in the previous version of Quartus II software, now provides automated partitioning in version 8.1, allowing more designers to leverage the productivity benefits of incremental compilation.

Quartus II software now also eliminates the need to modify gated clocks manually by automatically converting gated clocks (as used in RTL intended for an eventual ASIC deployment) to functionally equivalent logic supported by the FPGA architecture. Automating these features allows design teams to focus more effort on value-added portions of the design.

Expanded device support
Altera launched its high-performance, high-density 40nm Stratix IV FPGAs in May 2008. To date, nearly 600 customers are part of Altera's Stratix IV early adopter program, and many have started designing Stratix IV FPGAs into applications across all of Altera's market segments using Quartus II software.

Version 8.1 provides an even greater level of support to these customers by adding Stratix IV pin-outs and support for a new Stratix IV FPGA speed grade offered in a low-cost package. The software provides added transceiver timing-model support, as well as support for 8.5Gbit/s transceivers, 1.6Gbit/s LVDS and 400MHz DDR memory. For designers targeting a HardCopy ASIC implementation, Quartus II software provides initial support for HardCopy IV ASICs.

New features

  1. SignalTap II Embedded Logic Analyzer!Finer data-sampling control speeds debugging and improves on-chip memory efficiency.

  2. Enhanced SOPC Builder Tool!

  3. New HDL templates enhance the speed and ease for which SOPC Builder can be used for intellectual property (IP) reuse.

  4. A new Avalon memory-mapped half-rate bridge is available for low-latency access for DDR SDRAMs.

  5. New operating system support!Red Hat Enterprise Linux 5 and CentOS 4/5 (32bit/64bit) are now included.

  6. Enhanced third-party simulation interface!The interface supports automatic compilation of library files for faster simulation setup.

  7. New Pin-Out Advisor!The advisor guides pin-out creation and interface with third-party board tools.

  8. Real Intent Verification Support!Real Intent's Meridian FPGA Clock Domain Crossing (CDC) software offers easy-to-use automatic clock intent verification to catch design errors and create confidence in reliable CDC operations.

  9. New and enhanced IP cores and megafunctions!Digital signal processing (DSP), memory and protocols accelerate development.

  10. Physical synthesis engine enhancements!Improve performance of timing-critical blocks in 20 percent less time on average than the previous version for faster timing closure.

  11. Synopsys Design Constraints (SDC)!SDC templates guide and accelerate timing constraint creation.

Pricing and availability
Both the subscription edition and the free web edition of Quartus II software version 8.1 are now available for immediate download ( The Subscription Edition is also available in DVD format by request (

Altera's software subscription program simplifies obtaining Altera design software by consolidating software products and maintenance charges into one annual subscription payment. Subscribers receive Quartus II software, the ModelSim-Altera edition, and a full license to the IP Base Suite, which includes 11 of Altera's most popular IP (DSP and memory) cores.

The annual software subscription is $2,495 for a node-locked PC license and is available for purchase at Altera's eStore ( or from authorized distributors.

- Clive Maxfield
Programmable Logic DesignLine

Article Comments - Quartus II software version 8.1 roll...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top