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Hypercore design tools upgrade multicore processing

Posted: 10 Nov 2008 ?? ?Print Version ?Bookmark and Share

Keywords:development tool? processor? multicore?

At the Multicore Expo Japan 2008, Plurality Ltd has launched the beta version of an extensive set of development tools for its HyperCore Architecture Line (HAL) of many-core processors.

Igor Pe'er, CEO, Plurality, said the tools will be responsible in the evaluation and widespread adoption of the company's technology. Many-core design "from tens to thousands of cores per processor" is widely recognized as the natural evolution of multicore processing. HAL processors, he added, will give the highest performance at the lowest price per watt per square millimeter of any chip-level shared memory machine currently available in the market.

"With multicore now mainstream, the future of computing inevitably will need massive parallelism performed on many-core processors," said Pe'er. He added that the architecture is seen as a general-purpose accelerator for applications with high degree of inherent parallelism, allowing HyperCore to act as an extension of the most popular processor architectures such as x86, PowerPC, and ARM.

HyperCore's distinct features
The HyperCore architecture has 16-256 cores and multiported L1 shared memory, where each core is equidistant from the memory. A key component of the architecture is a hardware-based, low-latency, high-throughput synchronizer/scheduler that manages the cores based on a task map and balances the load among the cores.

The synchronizer/scheduler ensures scalable performance that enables nearly linear speedup, regardless of the number of cores in the processor. Among the many applications suitable for the HyperCore processor are image and video processing, video surveillance, gaming, network processing, security and software-defined radio.

The HAL toolset includes a cycle-accurate simulator that runs on an x86 platform (Linux and Windows OS); a GCC cross-compiler (ver 4.0.1); GNU Binutils ver 2.18; a cross-debugger that works within the Eclipse development environment; and an emulator supporting Linux and Windows native environments.

What the device offers
Pe'er said the tools provide a gradual approach from exploring parallel decomposition with the emulator to precise evaluation of the performance of a 256-core system with the simulator.

Plurality's serial-like task-oriented programming model helps developers to easily write code for computations that are offloaded from the main processor. It eases the recompilation of serial code to parallel code and assures intuitive parallel programming of new applications.

He added that the many-core development tools are currently being evaluated at the University of Otago in Dunedin, New Zealand. Several labs in the Electrical Engineering department at the Technion, Israel Institute of Technology in Haifa, Israel also are checking the tools.

He noted that Plurality is producing acceleration boards that interface to a main CPU via a PCIe connection and AMD's HyperTransport link. The company is a partner in AMD's Torrenza initiative, which helps hardware makers other than AMD to connect a coprocessor to an open CPU slot on the AMD Opteron 64 via its HyperTransport link.

The beta version of Plurality's development tools is available now at no charge and can be downloaded from the Plurality Website.

Pe'er said Plurality will introduce an FPGA-based 32-core evaluation board in Q2 09. A 64-core chip (HAL-64) will be launched during 2H 09, along with an acceleration board that includes the HAL-64 processor.

- Bernard Cole
EE Times





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