Clock networks in the PolarPro devices

As designs targeted for FPGAs continue to increase in complexity and size, the ability to provide flexible clocking to various logic blocks becomes critical.

Poor clock networks (which are inflexible, prone to high skew, contain high path delays, and allow only a few number of clocks to be placed on the network) can prevent complex designs from being implemented on FPGAs. Even if some designs can be implemented, clock skew, power consumption, and poor routing can severely hinder their performance.

The QuickLogic PolarPro devices address this issue by providing efficient clock routing throughout the chip using global and quad-net clock networks.

This application note discusses the routing structure of the clock networks, the logic blocks and ports that each clock network can drive, and the use and advantages of each clock network.

View the PDF document for more information.