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Expanding the payload with National's FPGA-link DS32ELX0421 and DS32ELX0124 serializer and deserializer

Posted: 18 Nov 2008 ?? ?Print Version ?Bookmark and Share

Keywords:serialize? deserializer? FPGA? application note?

High data payload, reaching across 10's of meters of low cost media, is stretching the current boundaries of high speed transceiver solutions. Whether the data is packetized for Fiber Channel at 4.25Gbit/s or two streams of HD video content are multiplexed in a single link, more markets are emerging to push the limits of current high speed data solutions.

National's family of FPGA-Link (DS32ELX0421 &DS32ELX0124) serializers and deserializers operate at serial data rates up to 3.125Gbit/s. They interface to a FPGA or an ASIC over a LVDS bus containing five data bits and a clock. By combining two serializers and two deserializers the line rate is doubled to 6.25Gbit/s and the payload is increased to 5Gbit/s. This mode of operation is called link-aggregation. This design note offers implementation details of link-aggregation.

View the PDF document for more information.





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