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Improved ADCs minimize input-drive conversions

Posted: 19 Nov 2008 ?? ?Print Version ?Bookmark and Share

Keywords:ADC? bandwidth? converter?

Two new ADCs from Analog Devices Inc. (ADI) provide 16bit conversions, 86dB of dynamic range, wide bandwidth and low power for applications in wireless infrastructure, as well as medical data acquisition, and other instrumentation designs. With a continuous-time, sigma-delta design that is positioned between the low-noise, limited bandwidth of successive approximation register approaches and the wider bandwidth but lower-noise performance of pipelined designs, these converters also has an input that looks like a simple 1k? resistor, thus simplifying and minimizing input-drive needs.

The AD9261 is a single-channel converter, while the AD9262 is a dual-channel converter. Both are 16bit, 10MHz bandwidth, 30MSps to 160MSps devices. Within each converter are a PLL clock multiplier, decimation filters, sample rate converters, and loop filter, which eliminate need for an anti-aliasing filter. The input is sampled after the loop filter while oversampling and noise-shaping reduce in-band noise. The two-tone SFDR for the AD9262 is greater than 87dBc with SNR of 84.5dB to 10 MHz (15dB noise figure). The AD9267, a related product, includes only the 640MSps modulator core and PLL clock multiplier, to allow designers to offload signal processing to an FPGA or processor.

- Bill Schweber
Planet Analog

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