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Wafer-level packaging achieves prominence

Posted: 21 Nov 2008 ?? ?Print Version ?Bookmark and Share

Keywords:3D? wafer? MEMS? IC Package?

Wafer-level packaging (WLP), the fabrication of the IC package directly on the wafer, is finally getting exposure after many years of promises, according to an expert in the field.

"While challenges remain for the technology, WLP is moving toward a new class of IC devices in the marketplace, such as 3D products, MEMS, among others," said Tom Di Stefano, president, Centipede Systems Inc., a supplier of test sockets and connectors.

Before, productivity gains in semiconductor fabrication have taken the spotlight away from the package. "Packaging has always had a low-technology 19th century feel to it: bending leads, stamping metal and smashing wires against hot pads to join them," Di Stefano said in his recent keynote speech at the Fifth International Wafer-Level Packaging Conference.

"WLP is a paradigm for making packages of many types by fabricating them in parallel on the wafer," he added. "WLP is a parallel processing approach to fabrication of a portion or the entire package directly on the wafer. We are not wire bonding packages or making individual leads. In WLP, we're fabricating leads on packages 50,000 at a time, driving cost down a learning curve," he noted.

The initial rapid advances in WLP were made in the small-die domain for a total dimension under 3mm. "From there, WLP expanded into a range of different package types, including MEMS, through-silicon vias and somewhat larger die sizes," Di Stefano said.

WLP holds promise for memory devices and CPUs, but growth in those areas has been delayed by several factors. Many chips are too large for WLP fabrication because of the thermal coefficient of expansion mismatch between the chip and substrate.

"Over the past 10 years, memory suppliers have tried to provide WLP parts, but have fallen off the track for two reasons: burn-in test/handling and the lack of a reliable solder test technology," he claimed.

Wafer burn-in has been considered necessary for WLP, certainly for memory parts, but that has stalled. "Rather than probing the whole wafer, one solution is to dice the wafer, discard the bad dies, put the good ones in a tray and test them with Precision Array Carrier Test (PACT)," he said. "PACT brings numerous benefits like low cost, standardized handling and a standardized form factor, which have been among the main issues in WLP for memory devices," he added.

- Mark LaPedus
EE Times

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