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Hypercore IP available for license

Posted: 05 Dec 2008 ?? ?Print Version ?Bookmark and Share

Keywords:processor HyperCore? shared memory 64-core? SoC?

Plurality Ltd has said that its Hypercore 64-core shared-memory processing engine is available for license in the form of intellectual property (IP). The company said it would be flexible on how licensing deals are constructed.

"We are seeking an initial licensing fee and per-unit royalties. Amounts are negotiable. I cannot reveal the fees that we expect to receive," a spokesman told EE Times.

By licensing the Hypercore, developers will be able to integrate the general-purpose accelerator into their SoC designs. The 32GIPS, 8GFLOPS 64-core processor acts as a performance extension to the processor architectures such as x86, PowerPC and ARM. The IP version of the Hypercore processor was announced at the IP 2008 conference and exhibition in Grenoble.

Shared-memory design
"Hyperore delivers performance that is tens-of-times better and at the lowest price per watt per square millimeter than any other chip-level, shared-memory machine currently on the market," said Igor Pe'er, Plurality chairman and CEO, in a statement. "With our IP, developers of SoCs, ASICs and GPPs will save huge amounts of time and money in bringing the incredible power of many-core processing to mass-market applications like graphics, image and video processing, video surveillance, gaming, network processing, security, and software-defined radio."

The Hypercore architecture includes a patent-pending, shared-memory design in which the tightly-coupled cores are equidistant from a many-ported L1 shared-memory. Each core can randomly and directly access this memory at every clock cycle without a bottleneck, the company claimed.

"Plurality clearly is a pioneer in the many-core world. They are helping to advance the adoption of many-core architecture by offering IP and future chips that will support a broad range of applications in an open development environment," said Markus Levy, president of The Multicore Association, in the same statement.

Plurality's 64-core design delivers up to 32GIPS and 8GFLOPS performance when operating at 500MHz in 65nm GP process. Using high-speed libraries, an IP block with 64 cores, 16 shared floating point and multiply-accumulate units and without memory occupies less than 12mm?. Power consumption per-core is 10mW. A 64-core design with 16 floating point units, 1Mbyte of shared data cache and 64Kbyte shared instruction cache consumes about 3W and occupies about 25mm?.

The cores are controlled by a patented hardware-based synchronizer/scheduler (U.S. Patent No. 5202987). The synchronizer/scheduler removes management overhead from the cores, eliminates the need for an OS, enables dynamic load balancing among the cores and facilitates task switching at very high rates. The synchronizer/scheduler supports a task-oriented programming model that facilitates the identification of parallel structures. The programming model is based on mapping the interdependencies among the identified tasks, each of which is sequential code.

In November, Plurality announced the introduction of a set of development tools, including a cycle-accurate simulator and a software emulator for the evaluation of an application written in C code. The company offers training, support and design services for the target process according to the customer's specific configuration. Plurality will offer IP packages with or without automatic caching, with or without floating point units.

The company will release an FPGA-based 64-core evaluation board in Q2 09. The company's first chipwith 64 coreswill be introduced on 2H 09, along with an acceleration board that includes the 64-core chip.

- Peter Clarke
EE Times-Europe

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