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Open source SystemVerilog solution rolls

Posted: 09 Dec 2008 ?? ?Print Version ?Bookmark and Share

Keywords:verification? solution SystemVerilog? open methodology verification?

Cadence Design Systems has released an open source SystemVerilog solution to help users include Synopsys Inc.'s Verification Methodology Manual verification IP (VMM VIP) as they adopt the advanced environments supported by the Open Verification Methodology (OVM).

Built on top of the OVM 2.0 release, the Cadence solution lets users run both OVM and VMM VIP within a single OVM environment, the EDA vendor said. The OVM environment configures the VMM VIP, which communicates using both OVM sequences and virtual sequences, and uses the OVM message utility, according to the company.

"The verification ecosystem has enthusiastically recognized the superior features of the OVM," said Michal Siwinski, Cadence verification solution and product marketing group director. "We are seeing a growing demand for assistance in adopting the OVM, especially given the tremendous breadth of Cadence's line of verification IP."

Cadence said the solution is available to all Accellera VIP TSC members as a proof-of-concept implementation meeting their requirements. The SystemVerilog source code and documentation are available immediately in the "Community Contributions" area of the OVM World site.

Cadence added six new verification IP products to its Incisive VIP portfolio, each designed to speed verification of designs based on the emerging Mobile Industry Processor Interface (MIPI) standard. The introduction of the MIPI VIP family is the latest in a series of new VIP to provide customers with OVM VIP, Cadence said.

- EE Times

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