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Altera sees growth in slowdown

Posted: 16 Dec 2008 ?? ?Print Version ?Bookmark and Share

Keywords:market growth? FPGA? programmable logic? PLD?

Daane: Market slowdowns present an opportunity to accelerate replacement of ASICs and ASSPs over the long term.

Despite economic difficulties across the chip industry, FPGA makers didn't have it so bad for Q3 08. Altera Corp. announced increases in sales and net income for Q3 08 over Q3 07. John Daane, president, CEO and chairman of the board of Altera, explains how market slowdowns can be growth opportunities, and describes the company's activities in Asia.

EE Times Asia: How did Altera achieve growth in Q3 08 despite general market slowdown?
Daane: Altera remains committed to its fundamental themes of growth, efficiency and shareholder value, and we are pleased to have achieved all three goals for a second consecutive quarter. Our 65nm devicesCyclone III FPGAs and Stratix III FPGAshad another strong growth quarter, with sales once again more than doubling sequentially.

Market slowdowns present an opportunity to accelerate replacement of ASICs and ASSPs over the long term. System companies tighten budgets and cancel ASIC designs, and semiconductor companies rationalize their product portfolios and eliminate ASSP projects. Nevertheless, system differentiation is still required, and in the absence of ASICs and ASSPs, PLDs become the product of choice. It is here that our efforts to design innovative new software and silicon products pay off for our long-term growth prospects.

How has Altera performed so far this year?
We are very pleased with our progress to date. Our new products are now 46 percent of our revenue, and sales of these devices have grown 52 percent year over year as we continue to replace ASICs and ASSPs.

In terms of market segments, we have seen the communications segment grow 24 percent year over year across 2G and 3G standards. We have also seen 25 percent year-over-year growth in the industrial segment, led by gains in the military, automotive and broad industrial markets.

Please tell us about the 40nm Stratix IV FPGAs.
Our Stratix IV devices are the industry's first 40nm FPGAs and incorporate a unique architecture combining low power consumption with high performance, high density and high-speed transceivers. To date, Stratix IV FPGAs have achieved record design engagements with nearly 600 customers in our early adopter program. This is more than twice the number of customers as any previous program. Customers use our Quartus II design software to design Stratix IV FPGAs into applications across all of Altera's market segments. We expect the first shipments of the Stratix IV devices by the end of this year.

We have gained share in the FPGA market in each of the last six years with products noted for their architectural innovation. With the Stratix IV family, we offer customers benefits that are even more attractive based on a combination of both architectural and process-node leadership. As development costs for competing ASICs climb and engineers are forced to use older process technology, the economics and performance of leading-edge programmable logic become significantly more attractive. By moving quickly to the 40nm node, Altera has placed the company in a strong position to compete for designs that were once the exclusive domain of ASIC-based solutions.

What about your multicore devices? Please tell us more about them.
Because our Nios II processor uses a soft core, all of our FPGAs and HardCopy ASICs have the capability to be multicore devices. The programmability of our FPGAs is a big advantage for designers considering a multicore device because it allows them to design a device that fits their exact performance and power needs.

We simplify the task of multicore designs through our Quartus II design software and SOPC Builder tool. This tool eliminates the manual system-integration tasks of IP blocks in an FPGA design. Designers can select functions from the Altera or third-party IP core libraries to include in their FPGA. SOPC Builder automatically generates interconnect logic and creates a testbench to verify functionality, thereby saving valuable design time.

In addition, because FPGAs have inherent parallelism, our devices compete well vs. other multicore architectures even without using Nios II processors.

What's the outlook for Altera next year? Any other new product developments?
We are looking forward to the continued rollout of our 40nm devices in 2009 and continued gain of market share in programmable logic, as well as the ongoing replacement of traditional ASIC and ASSP sockets.

How did SOPC World turn out?
The SOPC World 2008 conference series was once again a success with events held in Bangalore and Delhi in India, and Shenzhen, Hangzhou and Beijing in China. The theme for this year's conference was "Power Down, Speed Up." During the keynote presentations, Altera executives outlined the methods and processes by which our devices deliver high speed and performance, while at the same time lowering power.

Joining Altera at these conferences was a number of our industry partners including The MathWorks, Aldec, Linear Technology, National Semiconductor, Freescale, Cadence, GiDEL and Echelon.

How is the partnership with TSMC coming along?
Altera and TSMC have enjoyed a strong partnership since 1993. From design through tape-out, together we're constantly refining the manufacturing process, resulting in chips that are rolled out successfully from node to node.

We're also redefining the foundry model. Traditionally, foundries and their IC customers worked in their respective areasmanufacturing process development and IC designsomewhat autonomously. This resulted in longer time-to-market and higher costs. Through a new integrated model, Altera and TSMC engineers collaborate on both manufacturing process development and IC design to achieve better and faster results that are, in turn, passed on to customers.

TSMC often qualifies its manufacturing process with Altera test chips because FPGAs are structured arrays, which are excellent for developing and qualifying a process. Test chips address design issues up-front while validating circuit design and process characteristics. For us, a faster manufacturing ramp means a faster production cycle for our devices.

Our collaboration with TSMC does not end at tape-out. We also work closely together on post-tape-out activities such as defect density improvements.

Aside from your relationship with TSMC, please tell us more about Altera in Asia.
Altera established operations in Asia Pacific over 10 years ago and the region has seen strong growth year over year. Altera is committed to the region, has offices throughout the region and has invested in a regional support center in Penang, Malaysia to serve customers worldwide. The facility in Penang has a large engineering group and is the company's largest site outside of the U.S. The company has also has a strong university program in Asia and has established 52 joint labs with leading universities.

Altera also enjoys strong customer relationships in Asia and we have received numerous supplier awards from Huawei, ZTE, Mindray and Samsung, to name a few.

Clue us in on Altera's environmental concern.
Whether it is developing new programmable devices that dramatically reduce power consumption in our customers' products or establishing extensive recycling and energy conservation programs in our buildings, Altera is committed to green business practices throughout the company.

- EE Times Asia





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