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Altera readies 40nm Stratix IV FPGA line

Posted: 17 Dec 2008 ?? ?Print Version ?Bookmark and Share

Keywords:Stratix IV 40nm? FPGA? DDR3?

Altera has announced silicon availability of the industry's first 40nm FPGAs. Targeting customers in a variety of markets, including communications, broadcast, test, medical and military, Stratix IV FPGAs are claimed to offer the industry's largest density, highest performance, highest system bandwidth, and lowest power among high-end FPGA solutions.

The first device available is the EP4SGX230, offering 230K logic elements (LEs), 36 embedded transceivers operating up to 8.5Gbit/s, 17Mbit of RAM and 1,288 embedded multipliers. With regard to the embedded transceivers, the Stratix IV GX provides excellent channel-to-channel isolation as illustrated below.

Leveraging the 40nm process node, the Stratix IV FPGA family is comprised of two variants, an enhanced (E) version and transceiver-based (GX) version. The Stratix IV family offers up to 680K logic elements, which is said to be over twice the logic capacity of competing high-end FPGAs, as well as performance that is 35 percent faster than competing solutions.

The devices also support DDR3 memory interface speeds of 1067Mbit/s. Stratix IV GX FPGAs feature up to 48 transceivers operating up to 8.5Gbit/s, enabling the development of next-generation, high-bandwidth communication infrastructure.

Lowest power
Featuring an advanced logic and routing architecture, and Altera's innovative Programmable Power Technology, the Stratix IV family is claimed to be the industry's lowest power, high-end FPGA. Programmable Power Technology enables every programmable logic array block (LAB), digital signal processing (DSP) block, and memory block to deliver high speed or low power, depending on design requirements.

Using this power-saving technology, customers can minimize power usage, while maximizing device performance. For additional cost and power savings, Stratix IV FPGAs provide customers a conversion to Altera's transceiver-based HardCopy IV GX ASICs.

Broad protocol support
Stratix IV GX FPGAs incorporate up to four hard intellectual property (IP) cores for PCIe Gen1 and Gen2 (x1, x4 and x8), and also support a wide range of protocols including Serial RapidIO, Gigabit Ethernet, XAUI, CPRI (including 6G CPRI), CEI 6G, GPON, SFI-5.1 and Interlaken. Stratix IV GX devices meet the rigorous jitter specifications of protocols like PCIe Gen2 and CEI 6G (critical for Interlaken).

The Stratix IV GX EP4SGX230 is currently shipping, with other family variants scheduled to ship in 2009.

- Clive Maxfield
Programmable Logic DesignLine

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