Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

USB 2.0 PHY on 40nm!What's the big deal?

Posted: 18 Dec 2008 ?? ?Print Version ?Bookmark and Share

Keywords:USB 2.0? PHY? 40nm?

By Navraj Nandra
The Eyes Have It

So what's the deal? If you look at USB 2.0 connector it has 4 pins: Dplus, Dminus, GND and 5V. For an embedded USB 2.0 PHY, the 5 V must be supported on the semiconductor technology that the rest of the chip uses. Today this is 65 or even 40 nm with 2.5 V or 1.8 V oxide. So the challenge is to build a circuit that can support 5V using a transistor, in the case of 40 nm, that has been only been rated to 1.8 V.

This requirement together with all the other electrical specifications is documented by the USB Implementers Forum. A couple of months ago we took our first USB 2.0 PHY test-chip design on TSMC's 40 nm process using 1.8 V native devices to the USB sanctioned testing lab. We ran the 5 V short tolerance test for the required 24 hours. We passed this test and met all the other electrical requirements - meaning that the USB 2.0 PHY is certified to meet all the electrical requirements including 5 V tolerance. (

So the question is´how did we do it? Well, come to my tutorial at the next SNUG and all will be revealed. (Well not quite all´just enough!)

- Navraj Nandra is part of the Synopsys His blog, The Eyes Have It, discusses all things related to mixed-signal PHY IP such as the latest trends, design challenges and anything that may be controversial.

Article Comments - USB 2.0 PHY on 40nm!What's the...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top