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200 Gbps silicon photonic integrated chip

Posted: 19 Dec 2008 ?? ?Print Version ?Bookmark and Share

Keywords:silicon? photonic? CMOS?

By Ansheng Liu
Research@Intel blog

In my blog of July 2007, I described the world first silicon modulator that encodes optical data at 40 Gbps or 40 billion bits per second. Today, I would like to share with you a silicon photonic integrated chip (PIC) that is capable of transmitting data at an aggregate data rate of 200 Gbps. Such an achievement represents a technical milestone towards the goal of realizing a single optical chip with terabits per second data transmission capability for future tera-scale computing.

As you may know, to fully exploit the computing power of multi-core and many-core computers, there is a need of high-speed and high-capacity communication network that can manage enormous data transport among the cores and memories. For high-performance computing, terabits per second transceivers may be needed in the foreseeable future. To achieve such a data rate, one needs to adopt various technologies such as wavelength division multiplexing (WDM), time division multiplexing (TDM), spatial division multiplexing (SDM), and their combinations. For example, WDM technology has been successfully used in today's optical fiber communication systems. So far these optical transmission systems have been usually constructed with discrete components such as laser, modulator, detector, and multiplexer, filter, and so on. Although such an approach has been proved to deliver high performance, it is not only bulky but also expensive.

Photonic integration is considered to provide a cost-effective solution for high-speed high data rate optical communication for future optical interconnects in computing industry. With monolithic integration of various photonic components on a single substrate, the resulting PIC would have much smaller footprint and be more cost effective because of less demanding on packaging and testing in the PIC as compared to the discrete component solutions. Because the CMOS electronics manufacturing infrastructures and processing technologies can be directly applied to photonics fabrication, silicon based PIC is particularly attractive for the future optical interconnect (I/O) applications. In the following, I describe a silicon PIC developed at Intel's Photonics Technology Lab , which is capable of transmitting data at 200 Gbps.

Fig.1 shows schematically a silicon PIC with WDM design. It consists of a 1:8 de-multiplexer (DEMUX), 8 high-speed silicon Mach-Zehnder modulators (MZMs), and an 8:1 multiplexer (MUX). As we can see from Fig. 1, a continuous-wave (CW) multi-wavelength laser beam is first split by the DEMUX. Each optical beam with a single wavelength then passes through a corresponding modulator. The CW light on each wavelength channel is amplitude modulated by the MZM so that the high-speed signal is encoded onto the optical beam. After the MUX, all 8 channels are combined in the output waveguide that can be coupled to a single optical fiber.

Fig. 1: A schematic of a silicon PIC with WDM design.

The key component of the integrated chip is the high-speed modulator, as the total data transmission capacity of the chip is fundamentally determined by the operation speed of the silicon modulator. To achieve >100 Gbps for the PIC, we adopted a similar modulator design as used for the first demonstration of 40 Gbps with a slight increase of the phase shifter length. Traveling-wave drive was used to obtain high bandwidth. On-chip termination load resistor was monolithically integrated with the modulator. For the MUX/DEMUX, we have chosen the cascading Mach-Zehnder Interferometer (MZI) design, although array waveguide grating or Echelle grating could be used.

Fig. 2: The PCB is also designed for DC bias control of MZMs and MUX/DEMUX phase tuning.

To enable high speed testing, the silicon chip is bonded to a printed circuit board (PCB) with low loss RF connectors. The PCB is also designed for DC bias control of MZMs and MUX/DEMUX phase tuning (see Fig. 2). In the high-speed testing, the differential RF signals from a pseudo-random bit sequence (PRBS) generator with [231-1] pattern length are amplified using a commercially available dual-output driver. The amplified single-ended output of 3.2 Vpp (6.4 Vpp differential) is combined with 2VDC using a bias Tee to ensure reverse bias operation for the entire AC voltage swing. The MZI modulators are biased at quadrature for all the high-speed measurements.

Before RF characterization, we tested the optical spectra of the integrated chip. We obtained relatively good channel uniformity (25 dB). For the data transmission experiment, we measured the eye diagram one channel at a time. Fig. 3 shows the 25 Gbps eye diagrams of all eight channels. We see from Fig. 3 that all channels show similar performance. Clear open eyes at 25 Gbps suggest that the single chip is capable of transmitting data at an aggregate bandwidth of 200 Gbps.

Fig. 3: Shown are the 25 Gbps eye diagrams of all eight channels.

Although the demonstration of 200 Gbps data transmission in a single silicon chip represents a milestone for future terabits per second optical interconnect, we note that such a demonstration was achieved with an external multi-wavelength laser source. To obtain a fully integrated transmitter with on-chip lasers, we will replace the DEMUX with a hybrid silicon laser array (link to hybrid laser page). With the demonstration of the silicon transmitter PIC as well as 40 Gbps Ge detector, it is possible to fabricate optical transceiver chips with terabits of aggregate data per second in the near future - truly enabling tera-scale computing.

You are welcomed to submit comments.

- Ansheng Liu is currently a principal engineer with the Corporate Technology Group at Intel.

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