ST, Synopsys collaborate on 32nm components

Synopsys Inc. and STMicroelectronics NV have joined efforts to enable the readiness of key components in a 32nm design flow, including ST's standard cell library for low-power and high-performance design, and the support of the latest route rules in Synopsys' IC Compiler Zroute technology.

Through this collaboration, ST said it becomes the first company to pre-qualify and deliver state-of-the art libraries internally for the high-k metal gate 32nm low-power International Semiconductor Development Alliance (ISDA) process, based on Synopsys' IC Compiler.

The chip maker explained it is then able to start implementing a complex DSP core test chip, which in turn allows validation-in-silicon to be carried out on a complete set of low power solutions for the ISDA process in the 2H 09.

Commenting on the collaboration, Philippe Magarshack, group VP at ST's Technology R&D, declared: "Synopsys' ability to quickly support the evolving 32nm route rules in IC Compiler's Zroute technology enabled us to validate our standard cell library routability and optimize it for the highest density. The availability of the first standard cell library is a key achievement towards 32nm readiness."

ST specified that, for library development, it used Synopsys' Cadabra product and, for route rule development, it chose Synopsys' Zroute technology.

In May, a project between ST and Synopsys resulted in significantly improved verification of analog IC design, the companies then claimed. As a result the chip maker said it had adopted Synopsys' HSIM-XA for its next-generation smart power devices targeting the automotive sector.

- Anne-Francoise Pele
EE Times-Europe