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Shanghai clears way for AMD's 45nm shift

Posted: 29 Dec 2008 ?? ?Print Version ?Bookmark and Share

Keywords:Shanghai? process node 45nm? Barcelona?

Advanced Micro Devices (AMD) moves to the 45nm technology node with the launch of its new Opteron server chip, code-named Shanghai. AMD is the third manufacturer to reach this milestone after Panasonic and then Intel.

AMD's previous generation 65nm Barcelona was the industry's first quad-core processor that also included 2Mbyte of shared L3 cache integrated on the same chip with a Northbridge memory controller. The Shanghai chip triples the L3 cache size to 6Mbyte, but all the basic building blocks were already incorporated in the 65nm Barcelona chip.

A quick glance at the Shanghai chip confirms one of its major selling points. It is pin-for-pin compatible with the Barcelona processor. This approach continues a long-standing AMD strategy to allow server manufacturers to maximize the life of their designs for many generations without new sockets and board redesigns.

Slimmed down footprint
Ripping open the chip's packaging offered the first glimpse into whether or not Shanghai was simply a shrink of the Barcelona die layout. Moving to the 45nm node certainly helped AMD to reduce the die footprint by over 10 percent to 253mm? despite doubling the total SRAM size on the chip from 4Mbyte to 8Mbyte. Each of the four processor cores has shrunk by almost 40 percent to less than 22mm?.

Shanghai is pin-compatible with 65-nm node Barcelona, thus allowing server vendors to maximize life of their designs for many generations.

Still, there is no question that Intel is at the cutting edge of process technology. Semiconductor Insights began analyzing 65nm parts from Intel in January 2006. AMD followed up in September 2006 with a dual-core Athlon desktop processor. In addition, Intel introduced its 45nm high-K metal gate (HKMG) process in November 2007!a year before AMD.

However, AMD process engineers are quick to point out their strategy of rapidly converting all of its manufacturing volume to the new node after its launch. In terms of architecture, the upcoming introduction of Intel's Nehalem chips will come more than a year later than AMD's design.

For servers, we all want our Google results to come fast so speed is important. Intel has a long history of pushing processor speed performance by designing transistors with high on-currents to drive fan-out gates quickly. In fact, Intel's 45nm HKMG transistors offer the best peak drive currents on the market today with 1.36?A/ ?m for nFETs and just over a milliamp for pFETs. Compared to Intel's speed-burners, a typical 45nm transistor on AMD's Shanghai is a lot less powerful.

More than speed
But there is more to the story than just pure speed performance. AMD has supplied comparison data that suggests servers based on the Shanghai chip consume up to 15 percent less power at peak processing load and 30 percent less at idle than Intel's current 45nm microprocessor. Data centers need to be kept cool so lowering server chip power reduces the air conditioning load as well. Tally those savings up over many server racks and you begin to add up some real savings.

AMD plans to introduce its version of a HKMG process developed in partnership with IBM midway through 45nm production. However, AMD's first 45nm device is manufactured using polysilicon gates with an oxy-nitride dielectric similar to Matsushita's UniPhier video chip!the first to use 45nm process technology. Just like AMD, Matsushita brought immersion lithography online to meet the scaling requirements of 45nm. In fact, UniPhier boasts the tightest metal pitches in a logic chip at 138nm.

AMD's goal was to shrink the physical dimensions and increase performance. Scaling transistors mean better performance, but most of the dimensional scaling at 45nm is related to gate and metal pitches rather than the length of the transistor's gate or channel. The minimum gate length on Shanghai is 38nm!a reduction of only 7 percent from the 65nm node. But the transistor performance is 19 percent better for the nFET and 23 percent better for the pFET compared to 65nm transistors. So how was this achieved?

Every last drop
The answer is optimization. AMD improved transistor performance by squeezing every last drop out of the performance-enhancing structures that were already in use at 65nm. The starting point was a silicon-on-insulator (SOI) wafer as opposed to bulk wafer technology used elsewhere. The rest of the transistor performance story relates to strain engineering.

nFET structure yields 19 percent better performance.

For nFETs, stress memorization stretches the n-channel first, which is enhanced later in the process flow by the addition of a nitride tensile stress liner. The liner itself is scaled down at 45nm to ensure the required strain is adequately supplied to the transistor channel to enhance electron mobility and subsequently increase the drive current. The gate stack design is modified as well with a new sidewall spacer design for 45nm.

The pFET performance improvement is more dramatic with drive current up to 660?A/ ?m compared to 510?A/ ?m on 65nm transistors. Again, this increased output current is the result of optimized compressive strain for the p-channel device. The new pFET design moves the embedded silicon-germanium source/drain regions closer to the channel!reducing the space by half! to maximize the transfer of stress thereby increasing hole mobility. Although shorter gate lengths are not driving the improvements, it is a reduction in dimensions that is allowing increased channel stress to provide the performance scaling.

Architecture and process
The transistor drive current for AMD's 45nm devices is much lower than the Intel HKMG transistors. But power consumption is quickly becoming a high priority for server chips. Our transistor benchmarking indicates that leakage current is less than one-third of AMD's 65nm process. It's also significantly lower than the Intel 45nm HKMG process. In fact, the Ion/Ioff ratio for AMD's pFET is nearly 10 times better than the Intel pFET.

Of course, controlling power consumption at the chip level goes beyond the transistor level with clock speed reduction or even powering down whole blocks of the IC.

Architecture and process technology are by no means the only considerations when selecting a microprocessor for a server box. Upgrade path, power consumption and the interaction with chipsets and software all come into play. However, it's clear that competition is driving innovation resulting in better products and more choices.

With a major architectural overhaul, Intel will be pushing server performance with its Nehalem chips, but AMD can maintain its "negawatt" lead with its power-saving transistor design.

- Don Scansen
EE Times





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