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Low-power design binds chips, software

Posted: 31 Dec 2008 ?? ?Print Version ?Bookmark and Share

Keywords:design low power? software chip? energy?

By Steve Carlson
Cadence Design Systems

Electronic technology is rapidly evolving. Last year's hot product is quickly replaced by something smaller, faster and with more bells and whistles, which is great.

Still, there's a nagging awareness that every new gadget consumes more energy, adding to the carbon footprintand these footprints seem to be getting larger. In fact, the energy consumption problem is so critical that it's impacting system reliability as well. It's high time we made system design more power efficient.

Electronic technology gives us the ability to stay connected to better manage our increasingly complex lives. But each one of these connected devices draws more power. If you look at the applications stack inside almost any wireless electronic device, you'll see that internally it's expanding at an astronomical rateclear evidence of both the value these devices hold in our everyday life, and of their thirst for power.

Even outside these wireless systems, there's a tremendous requirement for power from traditional gridded power arrays, to support the transmitters and data centers that move data traffic around the world. It's been estimated, for instance, that one highly popular multi-user PC game in Asia alone uses the electrical equivalent of three power plants every day to support its players.

Power issue
While these applications and devices represent the leading edge in hardware and software deployment today, as incredible as it may seem, they are still very inefficient from a power consumption standpoint. Every hardware and software design in development today could draw less power. That means digital music and video players, handsets, data centers, laptops, PCs, workstationseverything.

Not surprisingly, everyone stands to benefit, as well. For example, by designing a cooler device, chip companies pass on a reduction in thermal energy on the chip. This, in turn, reduces the risk of product failures, enables smaller, less expensive packaging, and provides for improved carbon and area footprints for the overall system. The net is a smaller, less expensive and more reliable end-product.

Unfortunately, a large percentage of the hardware already in today's data centers and embedded platforms will probably remain there for some time. This means the opportunity to create power efficiency must come from both the chip level and the software managing the systems.

The upside is that there is still a lot of room for improvement here, as well. Many of these systems were designed without power efficiency as a key requirement, so even incremental improvements will create significant benefit.

Collaborative and coincident
For the future, software and hardware design must be collaborative as well as coincident. Engineers in these two disciplines must find ways to communicate their requirements and constraints, as well as incorporate energy efficient design techniques with little or no risk.

A common specification backbone that can serve as the lingua franca between the teams is, of course, one of the essential elements necessary for a more parallel and collaborative product development methodology. Further, power analysis capabilities must be pushed forward in project time, to enable energy optimization trade-offs between the teams. Verification technologies are an essential risk reduction strategy, particularly when deploying aggressive power reduction techniques.

Connectivity is here to stay, but that's only the starting point for chip and systems designers. The need for power efficiency will drive the hardware and software industries together and serve as the basis for a system-level design discussion. It's up to us to make sure this discussion produces meaningful results.

- Steve Carlson is vice president of marketing at Cadence Design Systems Inc.

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