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Studies address process variability issues

Posted: 25 Dec 2008 ?? ?Print Version ?Bookmark and Share

Keywords:variability process? semiconductor industry? CMOS?

CMOS device process variability remains one of the most acute problems facing the semiconductor world, particularly at the 45nm node and beyond, according to presenters at the International Electron Devices Meeting (IEDM).

Random defects were the primary cause of manufacturing yield loss up to the 130nm node, when layout systematic effects became more critical, according to a paper presented by Andrez Strojwas of Carnegie-Mellon University and PDF Solutions Inc. But more recently, Strojwas said, due to challenging product performance requirements and increased process variability, parametric yield losses have also become significant.

Strojwas's paper, "Taking the next step in Moore's Law: Design's turn to enable next technology node," prescribed a regular layout methodology for 32nm and below, including the creation of a design fabric with a limited number of "printability friendly patterns" that enable the co-optimization of circuit, process and design. This approach calls for limited layour contacts and construct-specific rules, Strojwas said.

This methodology, known as pdBRIX, was originally developed by startup Fabbrix Inc., which was backed by Carnegie-Mellon. Fabbrix was acquired in May 2007 by PDF Solutions, which markets the technology under the name pdBRIX.

Some have argued that so-called restrictive design approaches like pdBRIX limit designers' creativity, forcing them to design within constraints established to ensure higher yield. Strojwas acknowledged this argument in his talk, but suggested that designers' creativity is already beginning constrained by process variability's impact on yield.

Strojwas said the adoption of high-k metal gate for 32nm would help reduce process variability, at least for one node. He said the pdBRIX methodology would enable single-pass lithography at the 32nm node. It has been widely assumed that the 32nm node would require double patterning lithography.

Statistical variability, tweaks
In another paper, Asen Aseov from the University of Glasgow stated that the most problematic process variability issue is the statistical variability introduced by the discreteness of charge and granularity matters in transistors with features of molecular dimensions. This issue already profoundly affects SRAM design, according to the presentation. In logic circuits, it causes statistical timing problems and is increasingly leading to "hard faults," the paper stated.

"Advanced simulation of statistical variability and reliability in nano CMOS transistors," co-written by researchers from the University of Glasgow and one from Spain's University of Santiago de Compostela, described simulation techniques for studying random dopants and reported a systemic quantum transport simulation study of atomic scale current variability.

A third paper, presented by Puneet Gupta of the University of California-Los Angeles, argued in favor of "tweakability," giving designers the flexibility to exploit power-versus-performance tradeoffs depending on use models. Transistor perturbations or tweaks that can be controlled and modeled in the electrical sensesuch as gate-length biasing and transistor shapingenable designers to improve leakage, timing and other benchmarks, Gupta argued.

"The more tweaks I have, it gives the designer the perception of a better single device, which essentially performs much better," Gupta said.

Gupta noted that tweaks of this nature would require penalties in terms of layout, characterization, modeling and physical design overhead. "Tweaks are not free," Gupta said. "But they are probably cheaper than engineering and manufacturing a new device."

Earlier, Takayasu Sakurai of the University of Tokyo presented a paper on technology/circuit collaboration for low-power LSIs. This paper argued that two recent trends for improving power efficiency in LSI systems3D integration and ultra low voltage, or "deep sub-volt" design. To be effective, he said, both of these approaches require a concept Sakurai termed technology-circuit collaboration.

- Dylan McGrath
EE Times





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