Top 15 challenges to conquer for 22nm

Most of the leading-edge logic papers presented during last year's International Electron Devices Meeting (IEDM) in San Francisco dealt with the 32nm node. IBM Corp. presented one of the few 22nm papers.

In fact, leading-edge chip makers are currently in 22nm R&D. So what are the big challenges involved at the 22nm node?

The team of expert analysts from Semiconductor Insights—Xu Chang, Vu Ho, Ramesh Kuchibhatla, and Don Scansen—came up with a list of top challenges for the 22nm node.

Here's a list of 15 challenges (and more):

1. Cost and affordability
Cost of research and development, process technology, design-for-manufacturing (DFM) and other pieces of the IC-production puzzle continue to soar. Here's the big question: Do product volumes support the economic equation?

2. Scaling
Scaling is nearing the limit. So do we start changing the channel material? So far, a lot of work is done outside the channel, thereby keeping it pristine. Many are looking at germanium for the channel, which has a lot of potential for the required bandgap.

3. Lithography
New technologies like extreme ultraviolet (EUV) and maskless electron-beam lithography will not be ready for production. 193nm immersion lithography will be extended to 22nm with the help of double patterning.

4. Transistor architecture
Planar devices will likely be extended to 22nm. Multi-gate MOSFETs like Intel's tri-gate transistor and IBM's FinFETs have significant challenges with parasitic capacitance, parasitic resistance, among others.

5. Bulk silicon or silicon-on-insulator (SOI)
Bulk vs. SOI? No clear favorite for 22nm —yet. Maybe both will be used.

6. High-k/metal-gate
Replacement gate integration approach will be challenging due to narrower gate lengths. Zirconium oxide will be required for the scaling down of equivalent oxide thickness (EOT).

7. Strain technology
Various technologies, including stress memorization techniques (SMT) and tensile stress liner, have been used and embedded Si-C may be needed to improve NMOS current drive. Embedded silicon germanium (SiGe), compressive stress liner and channel/substrate orientation will be needed to boost PMOS performance.

8. Interlayer dielectric
Ultralow-k dielectric or air gap technology will be required as well as new barrier materials for copper. Further reduction of ''K'' value from 2.6 to 2.2 will be necessary to reduce coupling capacitance. Porous carbon-doped oxide materials will be needed.

9. Ultrashallow junctions for NMOS and PMOS
Ion implantation, coupled with flash and spike anneal, will be required.

10. Advanced liner for copper interconnect
Advanced liner and capping layer will be needed to improve the performance of the copper interconnect.

11. Parasitic capacitance and resistance
This will be very challenging. Optional processes may be needed, including elevated source/drain, advanced silicide, metallic source/drain and damascene copper contact.

12. Embedded memory
Zero capacitor RAM (ZRAM) is actively researched, but it will not be ready for production. Conventional 6T SRAM will be extended to 22nm.

13. Device circuit interaction
This will be very challenging: litho-friendly circuit layouts, process variation vs. circuit performance, DFM, among others.

14. Variability
Challenges seen for line-edge roughness of the gate, channel impurity control and static noise margin in the SRAM.

15. Reticle and wafer inspection
Killer defects an issue. Overlay a challenge at 22nm.

Other challenges to watch:

1. Mobility enhancement—Will remain important at 22nm.

2. Short channel effect—Advanced co-implant and annealing processes required.

-Mark LaPedus contributed to this report.

- Xu Chang, Vu Ho, Ramesh Kuchibhatla, Don Scansen
Semiconductor Insights