Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > FPGAs/PLDs
?
?
FPGAs/PLDs??

HardCopy II ASIC fitting techniques

Posted: 13 Jan 2009 ?? ?Print Version ?Bookmark and Share

Keywords:ASIC? II HardCopy? II Stratix?

Engineers often use a flexible, reprogrammable Stratix II FPGA for prototyping a project, and then transfer the design to a faster, more economical HardCopy II ASIC for mass production. This application note describes some possible design considerations and solutions for fitting a Stratix II FPGA design into a HardCopy II ASIC.

HardCopy II ASICs are low-cost, high-performance 1.2V, 90nm ASICs with pinouts, densities, and architectures that complement Stratix II FPGAs. HardCopy II ASIC features, such as phase-locked loops (PLLs), memory, and I/O elements (IOEs), are functionally and electrically equivalent to the Stratix II FPGA features. The combination of Stratix II FPGAs for in-system prototype and design verification, HardCopy II ASICs for high-volume production, and the Quartus II design software, provides a complete, low-risk ASIC solution.

View the PDF document for more information.





Article Comments - HardCopy II ASIC fitting techniques
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top