Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Pulling bits out of the "soup" more on high speed receivers

Posted: 12 Jan 2009 ?? ?Print Version ?Bookmark and Share

Keywords:receivers high speed? ADC?

By Navraj Nandra
The Eyes Have It

Further to my last entry on using ADC's in high speed receivers, I did get a few comments.

One viewpoint is that all receivers are ADCs. The question is how many levels? The more levels one has, the more digital processing that can be done (DFE for example). The issue becomes one of area and power vs performance, and it isn't an easy one because if you are willing to burn more area and power for performance, are you sure adding bits to the receiver ADC gives the best return on the investment? Consuming more power needs to be questioned. If a 2-bit ADC doesn't consume more power than a 1-bit, then you built the 1-bit converter wrong. Receiver designs are certainly moving toward more complex topologies for the high-end applications.

Disk read Channels used to be binary "DFE". Now all of them use an ADC based approach. The question is whether the future of backplane links will likewise head toward ADC type processing. This is unlikey to happen in the next 5-10 years. Obviously, there are many aspects of an ADC that are nice, for example: technology porting of a logic macro, testability and repeatability.

All of this is sounding a little like the "to sample or not to sample" debate. At the chip-level there is a ways to go before it will make sense, but in the backplane where you have such widely varying channels (both loss and discontinuities), I could see hitting an inflection point soon.

There was a lot of discussion a few years ago with respect to PAM vs Binary NRZ for the 6-10Gb/s speeds. It all comes down to whether you're better off at half the frequency, but 1/4 the signal. It can't just be a tie, either, because there's a lot of simplicity in a single threshold (binary) system that gets WAY more complicated with multi-level. ADC + DSP power dissipation was also an issue. Even today the best 1000Base-T implementations are more power than a typical 10G serdes channel (solving different problems, of course, but there are technology parallels). If you combine all the stochastic, discontinuity, and variable channel loss of backplanes, the tradeoffs start to look a lot closer at 20+Gb/s. You certainly have better options with signal processing for pulling the bits out of the soup!

- Navraj Nandra is part of the Synopsys OpenCommunity.org. His blog, The Eyes Have It, discusses all things related to mixed-signal PHY IP such as the latest trends, design challenges and anything that may be controversial.





Article Comments - Pulling bits out of the "soup"...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top