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Clock networks in the ArcticLink solution platform

Posted: 15 Jan 2009 ?? ?Print Version ?Bookmark and Share

Keywords:clock network. ArcticLink platform? ASSP? application note?

The ability to provide robust clocking to various logic elements in a device is critical. Poor clock networks are inflexible, prone to high skew, contain long path delays, and limit the clock loads that can be placed on the network. These issues can prevent the implementation of complex designs. In addition, performance can be severely hindered by clock skew and poor routing. The QuickLogic ArcticLink solution platform addresses these problems by providing efficient clock routing throughout the chip.

This application note discusses the routing structure of the clock networks, the logic blocks and ASSP ports that each clock network can drive, and the use and advantages of each clock network.

View the PDF document for more information.

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