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RLDRAM II memory interface for Virtex-5 FPGAs

Posted: 23 Jan 2009 ?? ?Print Version ?Bookmark and Share

Keywords:DRAM? memory? interface? FPGA?

DDR reduced latency DRAM (RLDRAM II) devices.

This application note describes how to use a Virtex-5 device to interface to Common I/O (CIO)

DDR reduced latency DRAM (RLDRAM II) devices. The reference design targets two CIO DDR RLDRAM II devices at a clock rate of up to 333MHz with data transfers up to 667Mbit/s per pin.

View the PDF document for more information.





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