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IP core enables next-gen 40Gbit/s systems

Posted: 23 Jan 2009 ?? ?Print Version ?Bookmark and Share

Keywords:IP interface core? systems 40Gbit/s Serdes? Lattice soft IP?

Lattice Semiconductor Corp. has announced the availability of the 40Gbit/s Serdes framer interface, Level 5 (SFI5) IP core for use in the LatticeSC and LatticeSCM (collectively known as LatticeSC/M) FPGA families.

The solution uses 17 Serdes channels in the LatticeSC/M devices, including the Lattice SFI5 soft IP core, and enables flexible and high-performance, next-generation 40Gbit/s systems.

The LatticeSC/M FPGA devices include 4-channels to 32-channels of high-speed Serdes capable of supporting data rates from 600Mbit/s to 3.8Gbit/s, and are said to be the industry's highest channel count Serdes-based FPGAs in production.

The flexiPCS physical coding sublayer block embedded in the devices supports an array of popular communications data protocols including SONET/SDH, Gigabit Ethernet, Fibre Channel, 10GbE (XAUI), PCIe and Serial RapidIO.

Additionally, the LatticeSC/M FPGA family also includes pre-engineered, fully standard-compliant embedded IP cores (SPI4.2, 1G/10G Ethernet MACs, PCI Express, memory controllers and CDR) implemented in Lattice's low-power masked array for cost optimization (MACO) structured ASIC blocks. These features, along with the LatticeSC's high-speed FPGA fabric and PURESPEED I/O technology, provide a platform suitable for a variety of next-generation transport applications.

The LatticeSC/M family (and the LatticeSC family, which does not support MACO functionality but is otherwise identical) provides five logic density points between 15K and 115K LUTs, 4-channels to 32-channels of embedded Serdes, embedded memory capacity from 1Mbit to 7.8Mbits of dual-port block RAM and general-purpose 2Gbit/s Purespeed I/O ranging from 139 to 942 I/Os. Each device also features eight analog PLLs and 12 digital DLLs and ample clock routing for optimum clock flexibility.

Lattice's MACO embedded structured ASIC blocks are available on LatticeSC/M FPGA devices and deliver pre-engineered, standard-compliant IP functions developed by Lattice to shorten end-system time-to-market. The LatticeSC/M families of FPGAs are supported by Lattice's latest generation of design tools, the ispLEVER ver 7.2 software design tool suite.

The SFI5 IP solution is available as a downloadable core from the Lattice Semiconductor Website. Key features of the IP bundle include:

??Full compliance to the Optical Internetworking Forum (OIF) Implementation Agreement OIF-SFI5-01.02;

??Data path uses 17 Serdes transceivers operating in 8bit only mode;

??Sixteen 16bit wide internal receive and transmit data paths;

??Supported through the ispLEVER IPexpress tool for easy user configuration and parameterization;

??Reference design suitable for use on the Lattice Semiconductor SFI5 evaluation board with Serdes channels running at 2.5Gbit/s;

??Reference design uses the Reveal Logic Analyzer to observe circuit operation;

??User-settable parameters to select the allowed number of framing errors for the deskew channel framer to go into or out of locked state.

The IP core and reference design are provided to customers at no charge. An evaluation copy of the bundle is available now and can be downloaded by registered Lattice design tool users with current maintenance agreements without charge from www.latticesemi.com/products/intellectualproperty.

- Clive Maxfield
Programmable Logic DesignLine





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