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Using the design security feature in Stratix III devices

Posted: 27 Jan 2009 ?? ?Print Version ?Bookmark and Share

Keywords:III Stratix? security design?

In today's highly competitive commercial and military environments, design security is becoming an important consideration for digital designers. As FPGAs start to play a role in larger and more critical system components, it is ever more important to protect the designs from unauthorized copying, reverse engineering, and tampering. Stratix III devices address these concerns with the ability to decrypt a configuration bitstream using the 256-bit Advanced Encryption Standard (AES) algorithm, an industry standard encryption algorithm.

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