Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

The bad stuff impacting DDR timing budgets and ways to avoid 'em

Posted: 29 Jan 2009 ?? ?Print Version ?Bookmark and Share

Keywords:blog? DDR? PHY SSTL? PLL DLL?

By Navraj Nandra
The Eyes Have It

The color coded scheme

Just returned from Asia and one of the questions often asked on this trip was: why bother with a DDR "PHY" when some SSTL I/O's with potentially a DLL or PLL slapped together with glue logic will do the trick of interfacing to an SDRAM? Oh, not forgetting the RTL for the actual DDR protocol that interfaces to the SoC bus. Wellthese SDRAM's are now running above 667 Mb/s and timing budgets on these high speed DDR memory interfaces can be impacted by a number of factors. That sentence usually raises eye-browsuntil I show the following picture. It is a good way of higlighting the various sources of noise and how they can eat into the overall DDR timing budget as the complexities associated with the timing and signal integrity of the memory interface has increased significantly with speed grades above 667 Mb/s.

Using DDR2 667 Mb/ps as an example (the corresponding bit time is 1500 ps), the total timing is composed of three budgets: transmitter, interconnect and receiver. Nominally, each of these three budgets account for about 33% of the total timing budget. JEDEC managed to scale down the DRAM contributors to the transmitter budget during reads, in addition to the receiver. Note that I picked a relatively slower speed, this problem gets much worse at 800, 1067 and 1600 Mb/s.

Using the color coded scheme:

Orange: During write, timing must account for SDRAM set up and hold. This is 100 ps for setup from the AC threshold and 175 ps for hold to the DC threshold, corresponding to 225 ps setup and hold. There is nothing you can do about this, remember this comes directly from the memory manufacturer's datasheet. The remaining budget is 525 ps for both setup and hold.

Green: Routing skews in package and PCB remove 35 ps. The remaining budget is 490 ps for both setup and hold.

Purple: transmit contributions from controller remove an additional 175 ps from the budgets. This includes control logic delay, skew, difference in delays of rising and falling edges, skew in clock path, PLL jitter, DLL jitter and DLL phase offset. The remaining budget is 315 ps for both setup and hold.

So all you have is the BLUE. The remaining budget must capture all of the timing uncertainties associated with signal integrity, crosstalk, PCB and package impedance mismatch, termination mismatch and frequency dependent losses. These effects impact DQS as well as DQ signals. Therefore, accounting for all the losses from the remaining budget, Tsu is 195 ps, Thd is 285 ps.

OK, so now we have an idea of all the bad stuff that is going on

The following techniques help reduce the losses:

  • Following package and die guidelines to minimize the skew between parallel lanes, starting from I/O to the output of the package

  • Using low jitter PLL, DLL and SSTL I/Os

  • Signal integrity simulations

  • The entire timing budget can be ensured by using a complete (PHY, I/O, controller) solution. The budget from the DRAM is already fixed, therefore only board, package, I/O, PHY and controller can be impacted.

Once all the dynamics and complexities of creating a high-speed memory interface have been understood, there are two options. One is an internally assembled kit. This requires assembly of individual I/Os, DLLs, PLLs and glue logic. System performance is uncertain until implementation is complete. High-speed logic and system integration is needed, as is an ability to run Spice modeling at a transistor level. A final requirement is an experienced signal-integrity engineer and models for trace layouts, sockets and DIMMs.

The other option (and here's my pitch!) is a fully-assembled DDR2 (or DDR3) memory PHY macro and controller from an IP vendor. Benefits include built-in design margin, increased certainty of system performance from a known design, reduced risk and development time, access to an experienced signal integrity team, and no requirement for a high-speed logic/system integrator.

- Navraj Nandra is part of the Synopsys OpenCommunity.org. His blog, The Eyes Have It, discusses all things related to mixed-signal PHY IP such as the latest trends, design challenges and anything that may be controversial.





Article Comments - The bad stuff impacting DDR timing b...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top