Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Joint research to reduce chip footprint by 10x

Posted: 30 Jan 2009 ?? ?Print Version ?Bookmark and Share

Keywords:footprint chip? collaboration research? reduce footprint chip?

Semiconductor Research Corp. (SRC) and Georgia Tech have joined forces for a $2.5 million collaboration among academic, industry and government that will create the Interconnect and Packaging Center (IPC) based at Georgia Tech. Results from the joint research are expected to enable a reduction in chip footprint by a factor of 10 while both decreasing power consumption and increasing performance.

The cooperative work of the center's participants is aimed at two objectives: creation of leading-edge technologies that connect billions of transistors on a chip called interconnects and improved ability of different chips to communicate with each other through enhanced packaging. Smaller, more powerful chips could be gained from such advancements.

"Transistors have made enormous progress in speed, performance and miniaturization, which places greater demand on the electrical connections between transistors, and between individual chips. The interconnect and packaging challenges are greater today than ever," said Paul Kohl, director for the IPC. "Georgia Tech has been a leader in creating new interconnect and packaging technologies for ICs, and we're very pleased to partner with SRC in launching the IPC."

Focus on 3D tech
To facilitate huge computing gains, about half of the IPC research will focus on new 3D technology. 3D can provide the semiconductor industry with viable options for stacking multiple chips vertically at room temperature while maintaining millions of inter-die electrical connections.

"The 3D approach to packaging is one of the most promising options for improving functionality and performance to help ensure the continued success of the semiconductor industry," according to Scott List, director of Interconnect and Packaging Sciences for SRC Global Research Collaboration (SRC-GRC), an SRC entity dedicated to extending the future of CMOS. "2009 is clearly a very difficult time for the industry, but continued sharing of research dollars provides a strong prescription for a brighter future."

The IPC begins immediate annual funding of $820,000 across its eight selected programs at Georgia Tech, Harvard, The University of Texas at Austin, Iowa State University and Nanyang Technological University (NTU). The international participation from Singapore's NTU marks a growing trend toward acceleration of progress through integration of the best global research.

SRC is providing $500,000 per year to IPC for three years. The State of Georgia is providing $320,000 for each of three years. The IPC will be based in the new Marcus Nanotechnology Building at Georgia Tech.

Per its charter, SRC will continue to take a lead role in collaborating on enhancements brought about by academic research associated with semiconductor design and manufacturing.





Article Comments - Joint research to reduce chip footpr...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top