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Serial BERT targets high-speed digital interfaces

Posted: 05 Feb 2009 ?? ?Print Version ?Bookmark and Share

Keywords:serial tester BER? jitter testing tolerance? digital interface high-speed?

Agilent Technologies Inc. announced that its new J-BERT N4903B high-performance serial BER tester (BERT) offers complete jitter tolerance testing for high-speed digital interfaces operating up to 12.5Gbit/s.

J-BERT N4903B enables design and test engineers to characterize and test compliance of next generation multigigabit serial bus devices such as PCIe 2.0, USB 3, QuickPath Interconnect, Hypertransport 3 and fully-buffered DIMM 2.

Features include the ability to emulate worst-case conditions by generating half-rate clocks with variable duty cycle and jitter for forward-clocked devices; most integrated and calibrated jitter sources with selectable random jitter with PCIe 2.0-compliant spectral distribution, single- and two-tone periodic jitter, spread spectrum clock (SSC) and residual SSC, BUJ, built-in ISI and sinusoidal interference; compliant jitter injection for testing the latest serial bus receivers such as PCIe 2.0, USB 3.0, SATA and DisplayPort; accurate TJ measurements with built-in CDR with tunable loop bandwidth; easier adoption to DUT by emulating electrical idle conditions and offering variable output voltage levels on supplementary outputs (trigger output and aux data output); faster execution of long test sequences with 60 block pattern sequencer; and upgrade path from Agilent's N4903A to N4903B, protecting investments.

Pricing of the serial BERT with built-in tunable CDR starts at $139,000 for the 7Gbit/s version and $179,000 for the 12.5Gbit/s version. It is available for ordering on March 2009.

Availability: Available for ordering March 2009

- Ismini Scouras

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