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A/D technology is ultrafast

Posted: 06 Feb 2009 ?? ?Print Version ?Bookmark and Share

Keywords:technology A/D? CHAIS IP ADC? CMOS 65nm?

Fujitsu ultrafast ADC IP

Fujitsu Microelectronics Europe's (FME) new ultrafast ADC IP is based on CHArge-mode Interleaved Sampler technology (CHAIS) for use in its standard 65nm CMOS process technology. This new high-speed ADC technology, claims the company, provides breakthrough performance levels in a standard CMOS process, enabling the integration of multiple ADCs with tens of millions of gates of signal processing logic and memory on a single chip. Initially targeting use in coherent receivers for 100G optical transmission, the technology is also applicable to high-end test equipment and any other system requiring high-speed data conversion and processing.

The CHAIS technology provides previously unachievable combinations of sampling rate, resolution and power consumption. These circuits avoid many of the limiting factors, such as restricted bandwidth and poor linearity, of conventional architectures to make ADCs with sampling rates of up to 100GSa/s feasible in CMOS for the first time.

Power consumption for the ADC is 2W typical per channel at 56GSa/s, which is unheard of for this performance level (ENOB>6)a half-speed mode provides 28GSa/s at 1W per channel. A 1.75GHz input reference clock is internally multiplied to provide ADC sampling clocks with less than 100fs total rms jitter and less than 500fs I/Q ADC skew.

The first production application of this ADC technology will be a single-chip DP-DQPSK coherent receiver for 100G optical networks, with 4-channels of 56GSa/s 8bit ADCs (I and Q signals, H and V polarisation) integrated with logic and memory to perform the complete receive PHY function when connected directly to the optical front-end. The ADC will initially be available in 2009. Other channel counts, sampling rates, resolutions and process nodes will follow according to market demands.

- Henri Arnold
EE Times Europe

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