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Integrated equalizer IC simplifies 10G SFP+ design

Posted: 09 Feb 2009 ?? ?Print Version ?Bookmark and Share

Keywords:CMOS? equalizer driver retimer IC? 10G Ethernet?


Phyworks has released the PHY1066 equalizer, driver and retimer IC that the enables host board designers to create 10Gbit/s Ethernet SFP+ receive and transmit interfaces for 'direct attach' passive twin-ax copper cables and 10GBASE-SR optical modules. Its small size, low power and minimal external component count also make it suitable for use in active copper cable assemblies.

Manufactured on a digital CMOS process, this highly integrated IC dissipates just 0.68W, less than 50 percent that of alternatives based on other semiconductor processes. The PHY1066's low power performance allied with its small footprint, flip-chip 36-pin BGA package means easier host board upgrades to higher port densities.

With its unique combination of programmable pre-emphasis, FFE/DFE equalization algorithms and integrated re-timer, the IC assures clean data delivery irrespective of cable thickness, reach and interference conditions. In trials, the PHY1066 has proven in 10GbE host interfaces to be capable of driving up to 15m of 'direct attach' passive SFP+ copper cable.

Phyworks' integration of robust and simple-to-use hardware algorithms removes the need for an external high-performance microcontroller and extensive firmware code development, saving on both system BOM cost and time-to-market.

The PHY1066 also features loss of signal and loss of lock alarms to enhance system monitoring, which is fed to a host controller by the driver's selectable 2-wire or SPI interface. The IC's PRBS and BERT functions can also be easily integrated as a part of link set-up and test procedures.

The PHY1066 is supported by a reference host design for evaluation purposes and is sampling now. Pricing is less than $10 in volume.

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