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Five ways to beat IC scaling roadblocks

Posted: 12 Feb 2009 ?? ?Print Version ?Bookmark and Share

Keywords:IC scaling challenge? lithography? 32nm?

Chip scaling will go on for the next several years, but there are several challenges that face IC makers.

Mark Bohr, Intel senior fellow and director of process architecture and integration at Intel Corp., outlined the challenges and potential solutions at the International Solid-State Circuits Conference. Bohr listed five major stumbling blocks!or challenges!for the 32nm node and beyond:

1. Patterning or lithography
Problem: Wavelength has been scaling at a slower rate than the IC feature size.

Current solutions: "Resolution-enhancement techniques, such as optical-proximity correction, phase-shift masks, and immersion lithography, have been introduced to bring us to the 32nm generation. But even with these enhancements, layout restrictions, such as unidirectional features, gridded layout and restricted line plus space combinations, have had to be gradually adopted."

Future solutions: "Double-patterning techniques and computational lithography are options being investigated to continue scaling to 22nm and possibly 16nm generations before extreme ultraviolet lithography could be ready to provide a significant wavelength-reduction and resolution enhancement."

2. Transistor options
Problem: Classical scaling ended in the early 2000s due to gate oxide leakage.

Current solutions: "Strained silicon, high-k dielectrics and metal gates have been significant innovations that have allowed MOSFET density, performance and energy efficiency to show continued improvements past when traditional scaling techniques ran out of steam."

Future solutions: "Substrate engineering makes use of wafers to improve p-channel mobility, but may not offer any advantage for n-channel devices. Multi-gate transistors such as FinFET, Tri-Gate and Gate-All-Around devices offer improved electrostatics and steeper sub-threshold slopes, but may suffer from higher parasitic capacitance and parasitic resistance.

"III-IV channel materials such as InSb, InGaAs and InAs are showing promise for providing high switching speed at low operating voltage due to increased carrier mobility, but challenges remain before a practical CMOS solution will be ready.

3. Interconnect options
Problem: New solutions are required to slow resistivity and other problems.

Current solutions: Today's processes use copper interconnects, low-k and other technologies to enable interconnect scaling at a rate of 0.7x per every generation.

Future solutions: "3D chip stacking combined with through-silicon-vias provides a high density of chip-to-chip interconnects. The downside of 3D chip stacking in this manner include the added process costs, the silicon area lost on the chip that has vias cut through it, and the challenges of delivering power and removing heat from the stack.

"Optical interconnects can address this bandwidth bottleneck if technologies can be developed that cost effectively integrate photonics with silicon logic. Using optical interconnects for on-chip signaling may be further off in the future due to the difficulties with scaling optical transceivers and interconnects to the dimensions required."

4. Embedded memory
Problem: High-density memory beyond SRAM is needed in today's devices.

Current solution: Traditional 6T SRAM cells are used in processors and other products.

Future solutions: "In additional to traditional DRAM, eDRAM and flash-memory options, floating body cell, phase-change memory and seek-and-scan probe memory options all provide greater bit density than what 6T SRAM cells can provide. But integrating a novel memory process together with a logic process on a single wafer without compromising one or the other could be difficult."

5. System integration
Problem: It is not sufficient to take smaller transistors as they become available to simply make more complex versions of the same system components.

Current solutions: "The new era of microprocessor scaling makes greater use of energy efficiency, power management, parallelism, adaptive circuits and SoC features to provide products that are many-core, multi-core and multi-function."

Future solutions: "As we ponder the best paths to take in doing higher level integration in the electronics world, we may consider examples provided by nature (such as the human brain).

Battling doldrums
Despite recent layoffs Intel announced plans to spend $7 billion to build or expand its fabs in the United States over the next two years.

The investment funds will be used to deploy its 32nm technology, which was recently rolled out. Intel is seeking to stay ahead of rival Advanced Micro Devices Inc., which intends to go fabless.

Intel said the investments will be made at existing manufacturing sites in Oregon, Arizona and New Mexico. It will support approximately 7,000 jobs at those locations, part of a total Intel work force of more than 45,000 employees in the United States.

Intel, while generating more than 75 percent of its sales overseas, performs roughly 75 percent of its semiconductor manufacturing in the United States. At the same time, about 75 percent of the company's R&D spending and capital investments are also made in the United States.

The first Intel processor to be built using 32nm technology is codenamed "Westmere," and will initially be used in desktop and mobile mainstream systems. Westmere production will ramp up beginning in 2009. Additional 32nm products will follow in 2010.

"We're investing in America to keep Intel and our nation at the forefront of innovation," Intel CEO Paul Otellini said in a statement released prior to a Feb. 10 speech on in Washington to announce the investment.

Still, Intel is also cutting manufacturing costs amid the economic downturn. The other shoe has dropped as the chip giant last month said it will close two older fabs and three IC assembly factories.

Intel also recently said it plans to close its IC-packaging plant in Shanghai, China!a move that would eliminate 2,000 jobs, according to reports.

Recently, Intel said Q4 08 net income fell to $234 million, or 4 cents per share, hit hard by a $1.2 billion loss on equity investments related to its interest in Clearwire Corp.

In the year-ago comparable quarter Intel posted net profit of $2.3 billion, or 38 cents per share. Revenue in the three months ended Dec. 27, 2008 sank to $8.2 billion, down 23 percent as previously predicted, from $10.7 billion in the comparable 2007 quarter.

- Mark LaPedus
EE Times

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