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DSP architecture aims at 4G

Posted: 13 Feb 2009 ?? ?Print Version ?Bookmark and Share

Keywords:architecture DSP? terminals 4G? Ceva transceiver?

DSP silicon IP licensor Ceva Inc. has started sampling to select customers a multimode communications processor targeting 4G terminals and infrastructure it claims offers the industry's best performance to date.

Dubbed the CEVA-XC, the programmable DSP architecture supports full transceiver processing for multiple air interfaces in software, including the emerging LTE standard class 5 and WiMAX II (IEEE 802.16m), alongside 3G, 3.5G, Wi-Fi, GPS and mobile TV.

"We have been working on this crucial architecture for 18 months, and in collaboration with major vendors of mobile terminals and infrastructure gear such as femtocells," Eran Briman, VP of corporate marketing at Ceva told EE Times Europe.

Briman added that the CEVA-XC has been designed to address the stringent power consumption, time-to-market and cost constraints associated with developing SoCs for such applications, and the architecture "has been benchmarked by several Tier 1 vendors of handsets, broadband wireless modules and wireless infrastructure gear."

The performance of the processor is said to be equivalent to 8-10 Texas Instruments C64x+ DSPs in terms of DSP efficiency, and to outperform the latest offerings from Analog Devices Inc. and Freescale Semiconductor Inc.

Fully programmable approach
The core also includes a novel power scaling unit to support multiple clock and voltage domains and low power operating modes, allowing developers to meet power limitations while using a fully programmable approach. "As such, we see this development as a hugely important opportunity for us," said Briman.

The CEVA-XC scalable and configurable architecture is said to eliminate the need for heterogenic architectures composed of multiple wireless coprocessors or accelerators that increase cost, time-to-market and software design complexity in wireless SoCs, according to Ceva.

The DSP core comes with a complete integrated development environment including an optimizing C compiler, emulators, ESL tools and comprehensive software libraries.

The design builds on the company's CEVA-X DSP architecture and incorporates up to four modular Vector Units into the CEVA-X framework to deliver processing power of up to 200 billion operations per second. This enables CEVA-XC to support multiple LTE/WiMAX channels in a single core and claimed to better any other DSP available today for wireless infrastructure applications.

The CEVA-X DSP is already deployed in HSDPA and WiMAX chips, and designed into cores powering four of the top five handset manufacturersNokia, Samsung, LG Electronics and Sony Ericsson.

The CEVA-XC incorporates 1, 2 or 4 Vector Units within the CEVA-X architecture. Each vector unit consists of a 256bit SIMD engine using 3-way VLIW and a large array of 16 MAC, arithmetic, logic and shift units. An optimized instruction set handles the requirements of wireless modems including matrix processing, MIMO detectors, filtering, complex data permutations and bit stream processing.

The core will come in different options and available at different timescales, with the single vector unit version, targeting handsets, scheduled to be available to OEMs and ODMs first.

The ultralow-power design optimized for mobile devices will be up to four times more power efficient than general purpose DSPs, according to Ceva.

The system-level power scaling unit enables speed and voltage scaling at high level of granularity including processing units, memory subsystem, TCM and caches.

One example given is that power consumption will be just 10mW for LTE compatible 50Mbits/s download for a device made in a 65nm process, with the promise of a 30 percent reduction on that if made with a 45nm process.

- John Walko
EE Times Europe

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