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40G building blocks showcased at ISSCC

Posted: 13 Feb 2009 ?? ?Print Version ?Bookmark and Share

Keywords:building blocks 40G? 40G networking? CMOS?

Engineers showed progress pulling transceivers and other building blocks for 40Gbit/s networking into CMOS at the International Solid State Circuits Conference (ISSCC).

NEC Corp. described a full 40Gbit/s transceiver made in a 65nm process. Fujitsu, Broadcom and others detailed other key silicon building blocks for 40G nets.

The NEC device consisted of separate transmit and receive chips, each measuring 4.9mm x 5.2mm and dissipating 2.8W. That compares to today's much larger SiGe transceivers that draw 10W and require fans.

'Best results'
The reductions in size and power mean the chips could fit into a 28mm x 21mm module capable of handling multiple networking standards ranging from 39 to 44G. Audience members from Broadcom and Finisar praised the work.

"It was a very impressive paper, the best results I've seen to date," said Christopher Cole, director of transceiver engineering at Finisar. "They have been working on this for years, but they still need to provide a more complete characterization of the chip," he added.

The device is aimed for use in NEC's own computer and communications systems, but is a long way from commercialization, said Yasushi Amamiya, a principal researcher at NEC Corp. Ensuring long term robust operation is one of the challenges ahead, he added.

Separately, Fujitsu described a 40Gbit/s serializer, a key component for a 40G optical transport module. It supports 20G long haul and 40G short reach modes for Sonet OC-768, SDH STM 256 and ITU G.709.

To create the chip, engineers had to build a 20GHz PLL with low phase noise yet a wide range. They also had to distribute that clock with reasonable power while optimizing chip timing in the face of process and temperature variations.

The 65nm chip consumes less than 2W and measures 4.2mm x 4.2mm. Getting the device to work optimally in the thermal and other operational requirements of a data center is the next challenge to creating a commercial product, said Koichi Kanda, the Fujitsu engineer who presented the paper.

Finally, two researchers from University of California at Irvine presented a full-rate 40G multiplexer built in 180nm CMOS. Prior designs used a half-rate approach and topped out at 34Gbit/s. Alternative 40G parts have been made in more expensive indium phosphide, GaAs or SiGe processes.

"Data multiplexers are key blocks in high-speed communications, and a full-rate architecture is desirable to reduce the deterministic jitter," said Ahmad Yazdi who presented the paper and is also a staff scientist at Broadcom.

- Rick Merritt
EE Times





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