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Intel: EUV litho roadblocks ahead

Posted: 25 Feb 2009 ?? ?Print Version ?Bookmark and Share

Keywords:extreme ultraviolet lithography? EUV? double-patterning technology?

A top technologist at Intel Corp. warned that a lack of mask inspection gear for extreme ultraviolet (EUV) lithography is threatening the technology's future viability in the market.

Intel, which outlined its lithography roadmap, also warned that current 193nm immersion technology with double-pattering techniques will soon run out of gas, possibly at 20nm or sooner. This will require new solutions like EUV, but challenges remain for this and other next-generation lithography technologies.

The microprocessor giant hopes to insert EUV at the later stages of the 22nm node, but it is more likely to use the technology at the 15nm node (26- to 30nm half-pitch) in 2013 or so. Originally, EUV was targeted for the 65nm node, but the technology has been pushed out due to the lack of power sources, resists, defect-free masks and other technologies.

"We are pushing hard on EUV," said Sam Sivakumar, Intel fellow and director of lithography for the chip giant, at an event hosted by Nikon Corp. "Significant progress has been made."

But besides the usual issues, there are more "technical gaps" in EUV. To enable EUV in mass production fabs, IC makers must get their hands on defect-free photomasks. The trouble is that the industry is far behind in the development and funding of EUV-based inspection tools, mask blank inspection gear and fab reticle machines, he said.

In terms of R&D, EUV inspection gear is projected to cost $150 million, blank inspection gear is about $50 million and fab reticle machines is $10 million. Right now, tool makers face a major downturn and R&D dollars remain scarce.

Intel is pushing other chipmakers and consortiums like Sematech to drive tool development. "We are working very hard" to develop the EUV inspection infrastructure, he said, but "we need more support."

The two main EUV tool developersASML Holding NV and Nikonare separately pushing EUV technology for the 32- or 22nm nodes. KLA-Tencor, Rave and others are working on EUV inspection and repair.

Reports have surfaced that Samsung Electronics Co. Ltd may attempt to use EUV for DRAM production at the 45nm node or below. But Intel, the big proponent for EUV, will not use the technology in logic for some time.

At 45nm, the chip giant is using 193nm "dry" scanners, reportedly from both ASML and Nikon. Recently, Intel rolled out the details of its 32nm process (56nm half-pitch), with initial devices expected to be shipped by year's end. The company also said it will spend $7 billion in fab upgrades for 32nm production.

At 32nm, Intel will insert its initial immersion scanners, that is, 193nm wavelength technology. At the node, the company will use single-exposure technologyand not double patterning, Sivakumar said. At 32nm, Intel reportedly will use one lithography vendor, Nikon, as previously reported.

Double-patterning alternative
Sivakumar said the chip giant is looking to move into the 22nm node (40nm half-pitch) by 2011. Like 32nm, Intel will use 193nm immersion scanners for 22nm. There is an outside chance that Intel will use EUV for the latter stages of the 22nm node.

But unlike 32nm, Intel will use some form of double-pattering techniques for 22nm, including pitch-splitting or spacer, he said. "We will look at both options," he said.

It isn't quite that simple. There are several flavors of the technology, each of which have their own, complex tradeoffs. In double-patterning, there are two or so basic techniques: litho-etch-litho-etch and litho-freeze-litho-etch. There is also a rival technology called spacer.

Following the 22nm node, Intel plans to develop a 15nm (26-to-30nm half-pitch) technology for the 2015 time frame. At 15nm, the company is evaluating EUV as well as 193nm immersion with doubling-patterning. Regarding EUV, "the question is whether it will be ready and how much will it cost," he said.

Intel is also looking at inverse lithography or sometimes computation lithography at that node. Then, in 2015, Intel plans to deploy the 11nm node (18-to-22nm half-pitch). Like 15nm, Intel is looking at 193nm with double pattering and EUV.

- Mark LaPedus
EE Times





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