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Plug and Play IP goal remains "elusive" or is becoming tangible?

Posted: 25 Feb 2009 ?? ?Print Version ?Bookmark and Share

Keywords:bloghop? IP plug and play? DDR2? USB? SoC?

By Navraj Nandra
The Eyes Have It

DesignCon's IP Selection panel was text summarized by EETimes, essentially painting the view that plug and play IP remains "elusive". Here is my view that this goal is becoming tangible.

A lot of this depends on the type of IP, completeness of the IP deliverables, thoroughness of the IP design methodology and the expertise of the IP design team. The last two points are not so apparent until you actually engage with the vendor. Starting with the "type of IP" there is a difference between non-standards based IP such as PLL's and data converters, where there is no standard spec and the integration deliverables need to be modified depending on SoC interface. Using PCI Express as an example of standards based IP, my point is that even though it is a very complex protocol from the digital link layer to the serdes based PHY, the IP can be designed such that it can be integrated by an engineer that is not an expert in the protocol or in mixed-signal. What a good third party vendor does, in order to make the IP drop-in (or plug and play), is to provide all the design views including detailed integration guidelines. The different lane configurations that are supported in PCI Express must be matched by the IP deliverables. Throwing a serdes technology that supports 2.5 Gb/s or 5 Gb/s speeds needed for PCI Express but without the digital link/transaction layer over the wall to a customer claiming certainly supports the panel's view.

The methodology used to create the IP deliverables is also very important: test-chips, compliance workshops, split lots to see the impact of process shifts on performance and silicon characterization. Competent IP vendors must also provide support for ESD and latch-up protection.

In terms of the IP design team's expertise, the most important criteria is that the IP must be designed like the rest of the (predominantly) digital SoC in a bulk CMOS technology, no special process options for on-chip inductors, for example. Designers building IP for SoC integration such as a SATA PHY, face different challenges to the designers of discrete SATA chips. I'm making the assertion that the discrete designer may not necessarily design good IP. Power, area, ease of integration, and production testability are the key care-abouts of the IP designer whereas the discrete designer is focused on performance.

Another point mentioned on the panel was the challenges of IP placement and interactions with the other IP blocks or the rest of the SoC. True, this is a challenge. The IP vendor cannot control where customers place the IP on their chips, this comes down to the IP design methodologyessentially what is done before IP is shipped to customers. At #LINKKEYWORD0#, for example, our test-chips have noise generators around the IP to ensure robustness in a harsh digital SoC environment, multiple lanes are tested with the complete protocol stack (PHY and transaction layers).

Making the IP easy to integration is part of the story. If you now have PCI Express on your chip how do you test it? We provide on-chip diagnostics and test vectors that enable our customers to do production testing using a conventional digital tester, eliminating the overhead of writing the test-program.

Good third party IP vendors have a roadmap aligned to their customer's future needs, for example at Synopsys we do this by working on the standards bodies like PCI-SIG and USB IF for the next protocols and the foundries for the latest technology directions. In addition to this, an understanding of various market segments ensures that a broad portfolio of IP that works together is supported. Taking "digital home" as a segmentthis market requires DDR2 or mDDR, USB 2.0, PCI Express and SATA in an LP technology. The enterprise market typically requires the highest speed protocols (PCI Express 2.0 or 3.0, DDR3 at 1600 Mb/s, SATA/SAS 6 Gb/s) in the high performance technologies.

Today we're offering a number of very powerful silicon proven IP building blocks supporting the above market segments, customers now have at their finger tips the ability to build systems-on-chip, the system engineering task is becoming more complex, but also offering more room for differentiation. I'm very optimistic in helping to make IP plug and play tangible.

- Navraj Nandra is part of the Synopsys OpenCommunity.org. His blog, The Eyes Have It, discusses all things related to mixed-signal PHY IP such as the latest trends, design challenges and anything that may be controversial.





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