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Deconstructing source-mask optimization tech

Posted: 04 Mar 2009 ?? ?Print Version ?Bookmark and Share

Keywords:source mask optimization? lithography? EUV?

The SPIE Advanced Lithography conference witnessed a war of words among vendors developing source-mask optimization (SMO) tools in hopes of extending 193nm immersion lithography to the 22nm node.

Lithographers have, for years, used various schemes and computational techniques to optimize the illumination source. Likewise, they have long been optimizing the photomask through tricks like reticle enhancement techniques (RETs) and phase-shift approaches. SMO tools are being offered and developed to optimize the source and mask in tandem in order to maximize image contrast in a scanner.

But some say the term is being used for marketing purposes by a number of companies hawking fundamentally different technologies. They liken the situation to that which occurred with DFM, a well-worn acronym that came to be used to promote any technology remotely aimed at design-for-manufacturing.

"DFM is a great analogy" for what is happening with SMO, said Timothy Farrell, a distinguished engineer in computational technology with IBM's systems and technology group.

A number of companies are either developing or offering for sale SMO tools, including IBM, Brion Technologies, Luminescent Technologies Inc., Nikon Corp. and Cadence Design Systems Inc.

But Farrell and an executive from Mentor Graphics Corp., which is working with IBM on SMO for computational scaling, said the work being done by other firms does not truly optimize the mask, instead focusing on optimization of the illumination source for use with a reticle incorporating standard optical proximity correction (OPC).

"Source optimization capability has been around a long time," said Charlie Albertalli, a marketing director at Mentor. "We are seeing people use the terminology source-mask optimization when what they are really doing is source optimization."

Source, mask co-optimization
Brion, which is owned by Dutch lithography vendor ASML Holding NV, rolled out this week a new product, Tachyon SMO, which promises to enable full co-optimization of source and mask. According to the company, the product leverages proprietary illumination capabilities and scanner models from ASML to optimize the source simultaneously with all patterns on the mask.

Executives from Brion acknowledge that the prior generation of Tachyon focused on source illumination and the use of model-based OPC, but say the new product emphasizes co-optimization and that there technology is not dissimilar to the work being done by IBM and its ecosystem partners, including Mentor and photomask maker Toppan Printing.

Moris Kori, president and CEO of Luminescent, said via email that the statements made by Farrell and Albertalli did not accurately characterize his company's technology.

Kori said Luminescent's inverse lithography technology offers the ability to optimize mask patterns in conjunction with illumination patterns, resulting in a free-form, composite or parameterized geometry for the source along with a simultaneously optimized mask pattern including elaborate assist features integrated with main feature corrections.

The IBM-Mentor work uses algorithmic routines and a series of linear optimization capabilities to generate a custom illumination source and a reticle, according to Farrell and Albertalli.

"To create a customized illuminator with the mask that goes with it is quite a different proposition," said Albertalli.

Brion's SMO technology, including the Tachyon SMO and previous Tachyon products, is already in use at major logic and memory chipmakers worldwide, executives said. They emphasized Brion's ties with ASML, which they say give them insight into the parameters of lithography scanners needed to ensure manufacturability.

"What we are focusing our efforts on is having a manufacturable solution with our knowledge of ASML scanners," said Keith Gronlund, senior product marketing manager for Tachyon SMO.

Kori said six major chipmakers in Europe, Japan, Korea, Taiwan and the United States are now using Luminescent's inverse lithography technology in production at 50nm and/or in development down to 22nm.

According to Brion, the accuracy of the AMSL scanner models ensures that the SMO output will transfer and image correctly on the scanner. Full-chip extension is performed through the generation of a process model in the standard Tachyon format for use in production OPC and verification, according to the company.

"There are many [SMO] concoctions," said Tom Pye, Brion's senior director of strategic marketing. "At the end of the day, you have to get to a solution that gets you to manufacture on the scanner. This tool does that."

IBM-Mentor collaboration
Farrell said IBM announced last year it would work to extend 193nm immersion lithography through computational scaling in partnership with Mentor and Toppan because the company believed extreme ultraviolet (EUV) lithography would not be ready for the 22nm node. Farrell said this week that IBM has seen nothing since to contradict that assumption.

EUV was originally targeted for the 65nm node, but has been pushed out several times.

There now appears to be a consensus that EUV technology will not be ready before the 16nm node at the earliest. EUV has been dogged by delays due to the lack of sources, resists and masks. Intel, long a proponent of EUV, sent signals earlier this week that it is not expecting EUV to be ready by the 22nm node.

Meanwhile, Farrell said the development of SMO tools is progressing well and that 193nm lithography with computational scaling is a legitimate candidate for the 22nm node. The data obtained so far looks promising for reducing design constraints, he said.

IBM and Mentor initially pledged to have SMO beta tools available in June, and Farrell and Albertalli said they remain on target to comply with that timetable. In addition to creating the SMO tools, the work also focuses on creating use models which will enable companies to put the technology into practice in manufacturing, Farrell said.

IBM does not intend for computational scaling to be a proprietary technology, Farrell said. The reason for working with Mentor to develop the tools is so that they can be made available to the broader market, he said.

Several papers authored by IBM researchers and partners at the SPIE conference dealt with SMO technology. One, "Experimental result and simulation analysis for the use of pixilated illumination from source mask optimization for 22nm logic lithography process," argues that for the manufacturing benefit of SMO to be achieved, the manufacturability, reliability and sensitivity of the custom illuminators used must be well understood. It presented data from studies with experimental prototype illuminators.

A number of other SMO-related papers were presented by other companies, including a paper presented by researchers from Nikon describing a study of the effect of SMO and its application to ArF exposure tools. According to an abstract of the paper, "A study of source and mask optimization for ArF scanners," Nikon researchers developed several prototypes of SMO software and contend that even restricted SMO is effective for expanding process windows.

Researchers from Brion and ASML presented a paper on SMO at another SPIE event last November. This paper presented a co-optimization SMO method and compared the results with the existing iterative optimization method, concluding that co-optimization is more suitable for new technology node and process development.

- Dylan McGrath
EE Times

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