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Achieve differentiation through IP reuse

Posted: 04 Mar 2009 ?? ?Print Version ?Bookmark and Share

Keywords:differentiation chip? reuse IP? design performance?

As long as the process technologists continue to make it practical to deploy an increasing number of gates, creative design engineers will find ambitious new ways to use those gates to build competitive advantage.

Platform-based design with heavy IP reuse will continue to proliferate as more functionality is included into tomorrow's chip, but differentiation through software alone falls short of power and performance requirements.

Leading edge semiconductor and consumer products companies will continue to differentiate their products beyond IP reuse with proprietary functionality implemented in hardware. To maintain their competitive edge, they increasingly turn to higher levels of abstraction and synthesis for creating these proprietary hardware blocks.

While it is certainly true that platform-based design and IP reuse reduces effort compared with creating new hardware in RTL, assembling existing IP blocks is not a complete strategy for creating new SoCs comprising tens of millions of gates. Ways to create custom hardware more efficiently than handwriting RTL are also needed.

Central technique
The idea of leveraging IP reuse to build larger SoCs is that a system or semiconductor company will construct their unique product by assembling pre-existing IP blocks and adding custom software. Certainly, this approach is emerging as a central technique to help tackle increasing design challenges, and reduce the design and verification effort compared with substantial new RTL development. However, new functionality must still be built in hardware to satisfy performance and power requirements, and a higher level of abstraction is needed to complete these designs and get to market before the competition.

The market strategy of many systems companies depends on differentiating their products by implementing advanced functionality to deliver a superior end-user experience.

Notable examples include: face recognition for improved auto-focus in digital cameras; proprietary image scaling algorithms for upscaling DVD players; and cellphone modems that can produce better voice quality and tolerate lower SNRs. Visit your local big-box electronics store, and you will see a wide range of image quality on the wall of 40-inch LCD TVs.

These visible differences result from the use of proprietary image-processing algorithms; the companies that can deliver the best picture quality are able to demand premium prices for their TVs.

In some cases, the key functionality can be implemented in software. In many cases, such as those cited, performance and power constraints require that these functions be implemented in custom hardware.

While outsourcing the design of new hardware blocks is one tactic to reduce the cost of new RTL development, many companies find that approach too risky for the "crown jewels" that their proprietary algorithms represent. They choose internal development in areas that they consider their core competencies. And they prefer to implement the key proprietary parts of their designs using their own employees behind locked doors and network firewalls.

Engineering teams at many leading companies have concluded that using high-level synthesis (HLS) for hardware implementation in the areas of their core competencies along with platform-based design for overall SoC construction is crucial to their success. They use this approach not only to improve the productivity of their design teams, but to allow their companies to field competitive end-user products.

They have adopted next-generation HLS tools for development of key subsystems up to millions of gates. In many cases, HLS is the only practical way to deliver the needed functionality, performance and power characteristics within the narrow available market window.

- Mike Meredith
VP of Technical Marketing, Forte Design Systems





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