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Interface design guide for STMicroelectronics Cartesio microprocessor

Posted: 06 Mar 2009 ?? ?Print Version ?Bookmark and Share

Keywords:microprocessor? ST Micron interface design? SDRAM? application note?

The STMicroelectronics Cartesio STA2062 microprocessor is a highly integrated SoC application processor combining host capability with an embedded GPS. The STA2062 target markets include vehicle and portable navigation (PND), telematics and advanced audio and connectivity systems. The STA2062 features an external dynamic memory bus that can be configured to interface with mobile DDR or SDR memory devices.

This technical note provides guidelines for interconnecting the STA2062 dynamic bus controller to two Micron 512Mbit mobile DDR SDRAM devices to achieve a 128Mbyte external dynamic memory without series termination resistors other than clock line parallel terminations. This technical note also describes some key features of mobile DDR technology, provides general guidelines for developing the PCB floor plan, and identifies considerations for optimal trace routing and decoupling.

View the PDF document for more information.

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