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Litho woes: R&D gap, downturn

Posted: 06 Mar 2009 ?? ?Print Version ?Bookmark and Share

Keywords:lithography? funding gap R&D? industry downturn? EUV?

It was a triple-whammy for lithographers at the SPIE Advanced Lithography conference as the industry continues to be plagued by an R&D gap, technology delays, and, of course, the lousy economy.

Experts at SPIE warned about an alarming R&D funding shortfall for the various next-generation lithography (NGL) technologiesextreme ultraviolet (EUV), maskless and nanoimprintcreating more fear, uncertainty and doubt about the insertion of these schemes for mass IC production.

Based on the troubling trends, NGL needs more funding or a large "stimulus package," warned Milind Weling, engineering director of signoff and silicon optimization for Cadence Design Systems Inc.

Some technologies like EUV remain delayed or on the ropes, leaving leading-edge chip makers to resort to an assortment of complex, costly and unpopular double-patterning schemes. And not only were there the usual and nagging issues with double patterning and NGLs, but the current and steep IC recession turned SPIE into gloomy event.

Business is simply terrible for the lithography and fab tool communities, causing some concern among analysts about the condition of the industry. Looking at the glass half full, the downturn could slow the roadmaps of various IC makers, giving the various NGL technologies time to develop and play catch-up with their promised timetables.

On the other hand, R&D budgets, and possibly key staffers, are being cut. During the downturn, some wonder if will there be enough R&D dollars to go around in order to finish a raft of incomplete NGL technologies.

Others also wonder which fab tool companies will survive the downturn. ASML, Canon and Nikon will likely survive, but many of the small, innovative NGL startups could fall by the wayside.

And in the short term, orders are drying up for lithography vendors. Worldwide lithography shipments are expected to drop from 544 systems in 2007, to 323 in 2008, to 184 in 2009, according to Nikon Corp., citing data from Gartner Inc.

Most believe the figure is too high for 2009, saying the industry is seeing the worst downturn in the history of semiconductor equipment. One industry source believes that lithography shipments could fall as low as 80 or so units in 2009, a staggering drop over 2008.

Some vendors are praying for a 2H rebound, but others aren't so sure. Frankly, the entire fab tool community is still "looking for the bottom" of the current downturn, said Risto Puhakka, president of VLSI Research Inc.

Regarding a common theme in lithography, Puhakka said there's an ongoing trend in the business: It's the word "tomorrow." Vendors continue to make various claims about NGL, but they say the technology isn't ready today and promise to deliver "tomorrow," he said. "It's always tomorrow," he added.

Eyes on double-patterning
Supporters of EUV, maskless and nanoimprint disagree with those assessments, saying they will be ready for the 22- or 16nm nodes. Until then, leading-edge chipmakers must resort to double patterning. At present, leading-edge chip makers are using 193nm immersion technology for 45nm chip production. Some are also using a combination of OPC, phase-shift masks and double-patterning.

Amazingly, optical lithography continues to defy the law of physics. 193nm immersion can be extended to the 15nm node (22nm half-pitch logic), thanks in part to double patterning, said Burn Lin, senior director of the micropatterning division at Taiwan Semiconductor Manufacturing Co. Ltd. Lin is considered the innovator behind immersion, it was noted.

In doubling-patterning, an IC maker is essentially doubling the process steps and creating two masks, thereby boosting production costs. There are also various flavors of doubling pattering: LLE, LELE, spacer and others.

Litho-litho-etch (LLE) may be cheaper than the rival litho-etch-litho-etch (LELE) method, but LLE uses newfangled processes that are somewhat unproven. LLE uses two lithography exposures and two resist layers to create smaller IC features. In comparison, LELE uses two lithography exposures and hard-mask etches to create smaller features.

A third method is called spacer or self-aligned double patterning. "Spacer is a double patterning technique that uses deposition, anisotropic (directional) etching and trimming to produce smaller features on chips," according to ASML Holding NV.

Leading-edge chipmakers may use one or more types of schemes, depending on the product type. So far, the most desirable technology is LLE, due to fewer process steps and cost.

TSMC's Lin said he prefers LLE, "because of cost." The NAND flash crowd, which is said to be leading the process technology race, is already deploying some form of a double patterning scheme, reportedly spacer or sometimes called self-aligned double patterning.

The DRAM community, which is lagging in process technology, is evaluating spacer and LELE, analysts said. On the processor side, it appears none of the candidates are terribly attractive due to cost and complexity.

LELE "is expensive," said Jongwook Kye, principal member of the technical staff at Advanced Micro Devices Inc. For spacer, "Applied (Materials Inc.) has some solutions, but it's not perfect. Spacer is great for very regular designs.


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