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Oscillator touts low BER at high-speed transfers

Posted: 09 Mar 2009 ?? ?Print Version ?Bookmark and Share

Keywords:crystal oscillator? duty cycle tight? DDR application?


From Maxim Integrated Products comes the DS4266 266MHz clock oscillator specifically designed for DDR memory applications.

The device guarantees tight duty-cycle output of 48 percent/52 percent, and delivers RMS jitter of less than 1psRMS (12kHz to 20MHz) and cycle-to-cycle jitter of 7.5ps (typ). It thus increases system-timing margins and enables an extremely low BER during data transfer at very high speeds. The DS4266's superb duty-cycle and jitter performance make it suitable for the most demanding DDR memory applications.

The DS4266 boasts a 55 percent smaller footprint than traditional SAW-based and third-overtone crystal oscillator designs, which generally are not specified for duty cycles better than 48 percent/52 percent. The DS4266 is a low-noise, LC PLL-based oscillator that is fabricated using Maxim's proprietary SiGe process.

The design of the crystal oscillator incorporates fundamental AT-cut crystal technology and does not employ an overtone crystal to achieve the high-frequency output. This approach eliminates the spurious modes of operation typically found in third-overtone designs, and improves overall stability over SAW-based oscillators (> 100ppm). The DS4266 also provides extremely low aging (The DS4266 supports LVPECL and LVDS output types. The device is fully specified over the -40C to +85C extended temperature range, and is available in a space-saving, 5mm x 3.2mm x 1.49mm, 10-pin LCCC surface-mount ceramic package. Prices start at $4.50 (10,000-up, FOB USA). Samples are available to speed designs.

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