Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > FPGAs/PLDs

Performing DAC operations with CPLDs

Posted: 06 Mar 2009 ?? ?Print Version ?Bookmark and Share

Keywords:operations DAC? CPLD? speaker audio?

A pulse-width modulator (PWM) is a common way of generating analog outputs from a digital component. A PWM replaces a DAC that generates analog voltage or current proportional to the digital input. As the name implies, a PWM generates a series of constant voltage or current digital pulses with pulse widths or duty cycles that are proportional to the intended analog strength. The series of modulated pulses can be converted to an analog voltage with a low-pass filter, but this is usually not necessary.

Figure 1 shows a typical analog signal and its corresponding digital PWM representation. In general, an analog signal has maximum amplitude, minimum amplitude and many levels in between. In contrast, the PWM only has two levels: maximum and minimum.

Figure 1: Shown is an analog signal and equivalent pulse-width modulation. (Click to view full image)

To convert from analog to digital, the analog signal first is sampled at a carrier frequency. For a given sample period, the area under the analog signal equals the area under the PWM pulse. The key principle behind the PWM is that a short pulse at maximum amplitude has the energy equivalent to a continuous analog signal at a lower amplitude. This simple equation determines the required sample frequency for a PWM circuit:


where FSAMPLE is the rate at which the analog signal is divided into digital packets, and FRANGE is maximum frequency of the analog signal to be reproduced by the PWM. In the case of audio, for example, this may be 4KHz for a phone or 20KHz for an MP3 player. The "2" in the equation comes from the Nyquist frequency, which is the accepted oversampling rate required to reproduce an analog signal from digital samples.

The next step is to generate a clock to drive the PWM granularity. The following equation determines the PWM frequency:


where FPWM is the clock frequency driving the PWM block, and R is the resolution. The resolution is typically a multiple of 2N (where N = number of bits in the digital data stream words). However, with the proposed MAX IIZ PWM, any resolution is possible.

Controlling light, sound, motion
The three most useful analog applications for MAX IIZ PWMs are an LED driver, audio output and motor control. These allow the CPLD to control light, sound and motion for the following functions:

??Light (control LED blink intensity to save power, display back-light intensity, tri-color LED color mixing);
??Sound (audio play back, audible warning messages, ringtones and sound effects, keyboard clicks and tones);
??Motion (motors, i.e. phone vibrators, game motion feedback, warning vibrations for controls, cooling fan control, keyboard tactile feedback; servos, i.e. analog control voltage, digital control pulse).

Figure 2 shows that it is easy to connect the CPLD to an LED, speaker or motor. Typically, a minimal number of external components are required. One misconception about PWM outputs is that they must go through some type of filter to convert the digital signal back to analog before it can be used. In the following examples, only the analog servo motor requires a filter.

Figure 2: Shown are circuits for converting the PWM signal to light, sound and motion. (Click to view full image)

A PWM controlling the light intensity is perhaps the simplest function. The human eye cannot detect a light flashing faster than 240Hz (a period of 4.2ms), yet it can distinguish thousands of levels of brightness. The percentage of time an LED is on during the 4.2ms can be as small as 0.01 percent, or 4.2?s, and the light still will be seen as dim but not blinking.

At 50 percent of the duty cycle, or 2.1ms, it is seen as half intensity, and at 100 percent duty cycle, it is seen as full intensity. A current-limiting resistor prevents the full intensity output from damaging the LED or the MAX IIZ I/O buffer. The CPLD has an 8mA I/O current setting that limits the output current and may eliminate a resistor from the BOM.

1???2?Next Page?Last Page

Article Comments - Performing DAC operations with CPLDs
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top