Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > T&M

On-chip IP set to replace ATEs

Posted: 11 Mar 2009 ?? ?Print Version ?Bookmark and Share

Keywords:memory self test? AMBIST chip? IP on-chip? ATE testing?

Cost of testing a chip varies between different products, but it is often a major portion of the production cost nonetheless. Most chips rely heavily on ATE for testing, the cost of which depends on the amount of time needed for a particular chip. ATE driven tests are also constrained by performance of the ATE and natural limitations of the test rigging!most chips can only be tested at slow test speed which is significantly lower than the actual designed operating speed.

To address these concerns, YFL elite introduces the Accelerated Memory Built-In Self-Test (AMBIST), an embedded on-chip IP designed to generate test patterns and compute a unique signature of test responses for verification.

AMBIST test patterns are generated with a secure hash signature standard (SHS) function; each test pattern generated is unique offering extremely low probability of test pattern repetition. The test patterns also demonstrate very high quality pseudorandom characteristics due to the quality of the SHS algorithms. In addition, each the test pattern generated may also be inverted if necessary and every memory bit can be covered with logic-0, logic-1, 1->0 transition and 0->1 transition tests. These features make the AMBIST well-suited for testing large memory devices.

The capabilities of AMBIST can be just as readily adopted as a Logic BIST. One way is to use the AMBIST as an on-chip ATPG for loading the scan-chains, eliminating the test-time consuming task of scanning external test patterns with ATE.

AMBIST further uses the SHS function to hash all captured response data or all written memory content to make a unique test-result signature!typically only 256 bits!for verification of the test result. The high quality of the SHS algorithms ensures that any erroneous test results in a test set would result in an incorrect test-result signature be generated; thus, whether or not a chip passes a particular test set can be verified just with the computed test-result signature. External test system only needs to read out the test-result signature from an AMBIST embedded chip to know whether the chip passed a particular test set.

The AMBIST-based chip is capable of being almost completely autonomous in the testing. It does not need any test vector inputs from an external test system, nor does it have to send all the test response data back to the external test system for verification. Simple initiation and the verification of the short test-result signature is all the test-time required of the external test system.

AMBIST typically generates 512 bits of test pattern at a time and takes less than 100 clock cycles for the task. Hashing of each 512bit test response data block also takes less than 100 clock cycles. A demo implementation of AMBIST on a FPGA, running the entire system on a single 20MHz clock and testing a 1Mbyte block of memory!with AMBIST generated test patterns and covering every memory bits with logic-1 and logic-0!took about 0.3 seconds test-time on-chip.

Article Comments - On-chip IP set to replace ATEs
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top