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Improved memory, cache boost DSP performance

Posted: 13 Mar 2009 ?? ?Print Version ?Bookmark and Share

Keywords:DSP? memory cache enhancements? processor?

Texas Instruments Inc. has released the TMS320C6457 DSP at speeds of 1.2GHz and 1GHz, delivering up to 30 percent more performance at one-third less the cost of current TI single core DSPs. The performance lift is due to several memory and cache enhancements, while the cost reduction is achieved through a smaller process node. These improvements provide system savings, greater efficiency and increased design flexibility for networking, military, imaging and industrial markets, in applications such as medical imaging, radar, industrial vision systems and test equipment.

Based on TI's 1.2GHz TMS320C64x+ DSP core, the C6457 delivers 9,600 (16bit) MMACS of peak performance for a cycle for cycle performance improvement of up to 30 percent. Performance improvements are achieved through 2Mbyte of on-chip L2 memory (up to 1Mbyte cacheable), faster 32bit DDR2 EMIF (667MHz) and memory, cache and bus architecture enhancements. This gives customers the flexibility to add more channels to their designs as well as increased headroom for additional application features.

In addition, the DSP features high-speed interconnect with Serial RapidIO (SRIO) and GbE MAC Serdes interfaces for efficient inter-processor communications. The device also has on-chip acceleration for telecommunications applications with two Turbo-Decoder Coprocessors and one Viterbi Coprocessor (VCP2). This increases channel decoding operations to offload the DSP core, allowing more channels on a single processor for system cost savings. In addition, the DSP has backwards code compatible with other high performance C64x DSPs to enable legacy code reuse for a significantly shorter development cycle and increased design flexibility.

TMX320C6457 samples are available in a 23mm x 23mm BGA package. Pricing for the 1.2GHz version is $146 and the 1GHz version is $112, both in 1K unit volume.

Developers can get started with the C6457 evaluation module that includes two on-board C6457 processors, high-speed DSP interconnect with GbE MAC and SRIO Serdes interfaces, embedded JTAG emulation with an XDS560T trace pod header and a board-specific Code Composer Studio Integrated Development Environment. It also includes several TI analog power management devices and a clock driver to improve system performance. Order entry is open for the TMDXEVM6457 at $1995.





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