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Design Guidelines and Timing Closure Techniques for HardCopy ASICs

Posted: 17 Mar 2009 ?? ?Print Version ?Bookmark and Share

Keywords:application note? ASIC hardcopy? closure timing techniques?

This application note covers topics from a timing closure perspective, for the successful migration to HardCopy ASICs from Altera's FPGAs. The first section covers metastability, synchronous and asynchronous resets, and synchronizing an asynchronous reset. This section also describes techniques for passing control and data signals across clock domains using a handshake mechanism and FIFO.

View the PDF document for more information.

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