Managing Designs with Multiple FPGAs

Managing designs that incorporate multiple FPGAs raises new challenges that are unique compared to designs using only one FPGA. There are several methods for managing multiple FPGAs in a single design, each of which has its pros and cons. One option is to create a master design, partition it into subsections, and assign one or two engineers per subsection. The challenge is not only how to account for signals that cross subsection boundaries, but also how to put the master design back together once the subsections are complete.

Another option is to work from the bottom up, handling each section as a separate design, and then, as with the first option, magically put the sections back together to form the master design. The problems with the second option are the same as with the first option except that the second option doesn't give the team the ability to examine the entire design at once. A third option is to give the master design to every team member and establish processes that mitigate the effects of inter-sectional changes. For example, when one designer makes changes that might affect another section of the design that a second designer is working on (where the change might not show up in his work space), a means of communicating these changes must be established among the design team. As you can guess, the challenge with this method is dependent on how rigorously the processes are being adhered to among team members so that when the master design is fully assembled, the team is able to converge on a solution with minimal rework.

This application note describes a split-and-merge method using the 7Circuits product from Taray that enables easier multiple FPGA design management. This approach helps mitigate the challenges previously described and can help ensure final design success.

View the PDF document for more information.