Using the DLL Phase Offset Feature in Stratix II and HardCopy II Devices

This application note describes how to implement the delay-locked loop (DLL) phase offset feature with Altera's Stratix II and HardCopy II devices. A DLL provides a process, voltage, and temperature (PVT) compensated delay that is used to phase shift the read clock from an external memory to align it with the center of the data valid window. The DLL phase offset feature provides a method to make fine non-PVT-compensated phase adjustments to the read clock from an external memory. If the circuit board or memory timing specifications are different than expected, you can use the DLL phase offset feature to optimize the read capture timing.

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