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FPGA solution enables low-cost PCIe bridge

Posted: 16 Mar 2009 ?? ?Print Version ?Bookmark and Share

Keywords:solution FPGA? Express PCI? Serdes IP core?

Lattice Semiconductor has announced the availability of a low-cost programmable PCI Express-to-High Speed Serial (HSS) bridge for the CAP12-120, a SOHO VoIP platform running on Intel architecture. This bridge design has been implemented in the LatticeECP2M FPGA. The solution uses the LatticeECP2M's low power, high-performance Serdes and a Lattice PCIe IP core.

The Lattice FPGA solution is used in the Intel CAP12-120 reference design, based on the Intel Celeron M 915GM processor and chipset. To address the voice, video and data communications needs of small and medium businesses and enterprises (SMB/SMEs), Intel has added two versatile yet affordable multisystem business gateway reference designs to its family of converged solutions platforms.

The Intel CAP12-120 is a proof-of-concept design for software-based IP-PBX/MSBG solutions that enables developers to build a converged communications device for up to 120 seats quickly and cost-effectively. These all-in-one-box solutions are capable of delivering a variety of services, and can be scaled and modified easily in software to meet the requirements of different customer premises. The fully integrated platforms include all the necessary hardware and software components for building cost-effective IP-PBX/MSG solutions, reducing the time, effort and development cost of these platforms.

The LatticeECP2M family provides an ideal FPGA platform for implementation of high performance serial protocols such as PCI Express and Gigabit Ethernet. The Lattice PCI Express IP, combined with Lattice's own high-speed Serdes and the low-power, high-performance LatticeECP2M fabric, provides designers a powerful platform for satisfying their high-performance bridging and co-processing needs. The flexibility of the LatticeECP2M fabric provides designers with a platform to develop a variety of applications while still meeting very aggressive cost targets.

- Clive Maxfield
Programmable Logic DesignLine





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