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Ease real-time solder joint fault detection in FPGAs

Posted: 13 Mar 2009 ?? ?Print Version ?Bookmark and Share

Keywords:solder joint fault? FPGA? PCB?

By Phillip Davies
Ridgetop Group

Solder joint faults can be described with a single wordpernicious. Solder joints connect the BGA package, containing an FPGA core, to the PCB. Without early detection, electrical anomalies caused by solder joint faults can result in the catastrophic failure of mission-critical equipment.

In order to prevent this, Ridgetop Group designed the Sentinel SJ BIST EPU (Solder Joint Built-In Self-Test Electronic Prognostic Unit). Part of a line of electronic prognostic solutions, SJ BIST provides real-time detection of solder joint faults in any operating FPGA for military, aerospace and automotive applications.

Solder joint faults can occur with FPGAs found in all types of commercial and defense products. When embedded in BGA packages, FPGAs become susceptible to failure from solder joint faults. The causes of solder joint faults cannot be isolated, early detection is difficult, and the intermittent failures escalate in severity until devices are rendered unreliable or inoperable. But, as so often seems to be the case, the problem is also the solution.

Types of faults
In operational devices, the primary contributors to solder joint faults are thermo-mechanical and shock stresses. Whether from vibration, torque forces, thermal cycling, material expansion or environmental stresses, the inevitable result is mechanical failure from cumulative damage. At the solder joint level, the damage is seen as a crack at the package/PCB boundary, although there are other possible points of failure in the solder joint network.

Statistical degradation modeling is the current method for predicting solder joint faults in programmed, operating FPGAs. However, since statistics vary and work best at trending large populations, statistical degradation modeling is a stop-gap solution, at best. With SJ BIST, Ridgetop provides a true tool for direct, in-situ measurement of prognostic indicators of faults in operating solder joint networks.

Since solder joint faults develop during manufacturing as well as in the field, SJ BIST can also be used to detect faults in uninstalled FPGAs. These manufacturing-related faults have their own set of detection challenges. Visual inspection is the current method used for identifying faults in the manufacturing environment. The primary disadvantage is the inability to test and inspect the solder joints.

Visual inspection is limited to the outer row while the board size and other surface-mounted components limit the view even further. As the array density of BGA packages increases, alignment tolerances become tighter. In fine pitch BGAs, there are thousands of solder balls with a 1mm pitch and a 0.60mm ball diameter. Under these conditions, pad misalignment and insufficient solder become causes of open and partial-open faults.

Even a 100 percent inspection by X-ray is not guaranteed to find solder joint faults when solder does not wet the entire pad. Another defect, involving the solder ball and paste wicking into a plated through hole, is not readily identifiable even with X-ray imaging. When enough solder wicks into a hole, an open fault is created for that lead.

As an in-situ softcore, SJ BIST is ideally suited for PCB-FPGA reliability testing in manufacturing for harsh environments.

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