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Solution supports on-chip power management

Posted: 18 Mar 2009 ?? ?Print Version ?Bookmark and Share

Keywords:management power? power on-chip? CPF Si2?

Cadence Design Systems Inc. has enhanced the Cadence Low-Power Solution to include support for new on-chip power management schemes enabled by the recently ratified Si2 Common Power Format (CPF) Version 1.1.

The enhanced solution spans the Cadence Encounter digital implementation and logic design technologies, and the Incisive functional verification and system design and verification technologies. The upgraded solution enables designers to more accurately model, analyze and debug power management components targeted for integration into large SoC designs. It includes macro modeling, seamless multilanguage support for IP integration and automated support of metric-driven verification methodologies such as those in the new Cadence Incisive Enterprise Simulation Environment.

The power macro-modeling capability enables more accurate characterization and analysis of power consumption within complex SoC IP. Additionally, the Cadence Low-Power Solution is completely generalized to enable a multitude of popular programming approaches to IP block integration, and delivers automated low-power design capabilities that extend well beyond implementation. The enhancements enable the IP block or SoC to operate as designed and within the power parameters required by the end application. One proponent of the enhanced CPF-enabled solution is Virage Logic. The company is consistently an early provider of advanced technology solutions, and over the years has broadened the power management capabilities of its SiWare Memory and SiWare Logic product lines. By using these products with the Cadence Low-Power Solution, SoC designers can more accurately analyze the benefits of the power management schemes in the context of their full designs.

"We recognize that support for macro modeling is essential for accurate power modeling in today's complex memory sub-systems," said Brani Buric, executive VP of marketing and sales at Virage Logic. "Our support of the Cadence Low-Power Solution enables us to deliver accurate power modeling to our mutual customers, which in turn enables them to develop complex, multifaceted SoCs that are fully capable of optimizing the low-power capabilities embedded in each IP block."

Another user of the CPF-enabled Cadence Low-Power Solution is Sonics. "Sonics provides our customers with low-power on-chip connectivity solutions that allow a high degree of power control," said Jack Browne, senior VP of marketing and sales at Sonics. "The inclusion of CPF 1.1 in Sonics products is an efficient way for designers to leverage these low-power solutions as designers integrate the IP back into their design flow."

Through the metric-driven Cadence Incisive Enterprise Simulation suite, the Cadence Low-Power Solution now enables automated assertion generation and automated low-power coverage for low-power intent verification; voltage-aware simulation and voltage tracking; full multilanguage support for low-power verification; and powerful new debug and visualization mechanisms.

Cadence Low-Power solution enables Fujitsu Microelectronics tape-out of 65nm WiMAX design.

- Paul Buckley
Power Management DesignLine Europe





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