Mux/demux for 100G networks to sample soon

Sierra Monolithics Inc. will start sampling in Q2 09 a range of 100G mux with clock multiplier unit (CMU) and demultiplexer with clock and data recovery (CDR) devices, with volume production scheduled for the Q4 09.

The first in a planned family of 100G chipsets, Sierra Monolithics said the devices will become key components for both 100G Ethernet and long-haul transport markets, which are experiencing huge growth.

The parts are targeted at both the short-reach data center and high-performance computing market, as well as long-haul and metro carrier networks that are carrying growing volumes of IPTV, Internet video, multimedia conferencing, HD programming, mobile video phones, on-line gaming, networked storage and other high-bandwidth transport payloads.

The industry is currently finalizing standards for 100Gbit/s data transmission, at the same time that 40G networks are moving into the general deployment phase, initially in router interconnect applications.

The IEEE 802.3ba group is on track to deliver a first cut of its standard for 40Gbit/s and 100Gbit/s Ethernet during the next few weeks.

A single 100G wavelength delivers ten times the bandwidth of current dense wavelength division multiplexing (DWDM) transport solutions—enough to support 800,000 simultaneous Internet calls. 100G standards are also expected to provide a convergence point between transport and Ethernet networks, by uniting WANs using SONET/SDH/OTN standards with LANs using Ethernet.

"After years of delay, network operators finally are moving on a wide scale to deploy 40Gbit/s DWDM in their networks," said Sterling Perrin, senior analyst with Heavy Reading. "But even as 40G begins to take hold, carriers already are anticipating a migration to 100G. The market eagerly awaits new products from suppliers of 100G chips, components and systems that will make 100G technically and economically viable."

Dubbed the Theta-100G parts, the initial devices include the SMI10021 10:4 MUX/CMU and SMI10031 4:10 CDR/DEMUX. Each uses the same fourth-generation, 130nm IBM 8HP BiCMOS SiGe process technology as the company's recently introduced 40G solutions.

The devices will come in a surface mount BGA package.

Why BiCMOS?
The company said BiCMOS is a natural choice for 100G because it is well suited for fast transistor switching requirements where low noise is essential. Bipolar SiGe results in higher gain, higher frequency and lower noise floor as compared to CMOS, allowing transmission systems to meet stringent eye quality parameters.

The Theta-100G chipset operates at 4 x 25.0Gbit/s to 28.3Gbit/s (100-113Gbit/s) and incorporates an integrated, dual-polarization quadrature phase-shift keying (DP-DQPSK) modulation precoder function that makes 100G networks extremely resistant to the type of impairments that are often encountered in older fiber.

Sierra says the inclusion of on-chip, selectable single- and dual-DQPSK precoding circuitry delivers high spectral efficiency, high optical signal-to-noise ratio sensitivity and robustness against dispersion. The DQPSK precoding function is implemented with dual I/Q-interleaved outputs (4x28Gbit/s) for dual-polarized (DP-DQPSK) applications.

The chipset will enable the development of 100G-capable line cards and transponders, and will support the 300-pin multisource agreement pluggable module definition and, in the future, smaller form factors.

- John Walko
EE Times Europe