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Synopsys CEO confident of IC rebound

Posted: 19 Mar 2009 ?? ?Print Version ?Bookmark and Share

Keywords:design tape-out? semiconductor rebound? IC design?

Delivering the keynote address at a user group event, Synopsys Inc. chairman and CEO Aart de Geus touted the company's new products and said the semiconductor industry would remain critical to the world after emerging from a recession expected to be long and deep.

De Geus predicted that economic conditions in the semiconductor industry would remain difficult for the next 12 to 24 months, but said there is no question that silicon technologies will play an important role in the future.

"I have no doubt that the semiconductor industry will continue to be an important pivot for mankind going forward," de Geus said.

Synopsys is very aware of that many companies and individuals are under enormous stress due to the global recession, de Geus said, and has taken steps to reduce costs for customers. But the company also continues to invest heavily in R&D so that its products will be ready to enable future designs, he said.

Asked about plans for Synplicity, the FPGA design and verification tool provider that Synopsys acquired last year for $227 million, de Geus said at least in the near term it would remain a separate business unit and that its Synplify Premier and other products would remain standalone.

But de Geus wouldn't rule out rolling Synplicity technologies into other Synopsys products in the future, saying the acquisition had brought side benefits to the tools such as alignment with IP and verification.

"We don't want to go to the mega solution where everything is put in and nothing is quite as good as before," de Geus said.

Design tape-out slowdown
De Geus presented data from a Synopsys Users Group survey showing that advanced design tape-outs have slowed in recent years. Whereas the industry crossed the 250 tape-out threshold for the 90- and 65nm nodes at two year intervals, according to the data, the 250th 45-/40nm design is expected to tape-out this quarter, more than two years since the 250th 65nm design taped out in Q4 06.

De Geus showed data from market research firm International Business Strategies (IBS) indicating that non-reoccurring engineering costs are growing at an alarming rate and are projected to pass $100 million per design by the 32nm node. The cost increase is being driven by a rise in software and verification costs, according to the data.

This cost increase is making it increasingly difficult to design chips for anything other than large markets. Investing $90 million in R&D on a design requires a market opportunity of at least $400 million, according to the IBS data presented by de Geus. The global recession is accelerating these trends, according to de Geus.

On the alarming rise in verification complexity and cost, de Geus presented data from the International Technology Roadmap for Semiconductors indicating that a 675 percent increase in verification complexity is required over the next seven years.

De Geus' presentation referenced Synopsys' acquisitions over the past three years of Synplicity, Virtio Corp. and ProDesign's CHIPit business unit as evidence that Synopsys is investing in hardware-software co-verification technologies in order to facilitate system prototyping.

New products
De Geus detailed Lynx, an automated chip development environment introduced by the company March 16. Lynx combines an RTL-to-GDSII design flow with productivity-enhancing features to accelerate chip development while mitigating the risks of designing at new process nodes. A Synopsys employee joined de Geus on stage to do a demo of the new tool.

In his presentation, de Geus also highlighted other recent Synopsys product innovations, including a 2-3X speed-up in design turnaround time from the latest release of IC Compiler, advancements in the Galaxy Implementation Platform, USB 3.0 IP cores and flexible multicore processing technology in the latest release of the PrimeTime static timing analysis tool.

Elsewhere at the ISQED conference, Synopsys announced Yield Explorer, a new yield management tool said to expedite the discovery and mitigation of yield limiters in leading-edge integrated circuits.

- Dylan McGrath
EE Times

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