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Power management for optimal design

Posted: 19 Mar 2009 ?? ?Print Version ?Bookmark and Share

Keywords:eSilicon? management power? design optimal?

By Prasad Subramaniam
eSilicon

Power consumption is becoming extremely important in electronics. With increasing emphasis in reducing energy consumption in products, system designers are required to take more care in managing their power budgets. As a result, chip power budgets are being slashed while maintaining cost and performance goals. Unfortunately, the migration to finer technologies is compounding the problem. First, leakage power increases significantly with finer geometries and is becoming a key component of the total power. In addition, the finer geometries do not provide the voltage scaling that was enjoyed by previous generations of technology. As a result, the power saving due to voltage scaling is no longer substantial. In addition, from a design perspective, chips in the new generation of technology normally see a major increase in features and functionality. Taking all these factors into account makes power management a significant challenge for most designers. An intelligent approach is therefore required for optimizing power consumptions in designs.

Basic operation

To understand power, we begin with the classic MOS transistor equations for the drain current. While these equations are only accurate for older technologies and do not take into account various effects introduced by the submicron geometries in modern technologies, they will serve well in understanding the overall behavior of the transistor.

Active Power:

In digital circuits, when the transistor is on, it is in the saturation region where the current Ids is governed by the following equation:

(1)

Where tox is the gate oxide thickness,
W is the channel width of the transistor,
L is the channel length of the transistor,
Vgs is the voltage applied between the gate and the source of the transistor,
Vth is its threshold voltage, and
k is dependent on the process technology.

The threshold voltage Vth is governed by the following equation

(2)

Where Vsb is the back-bias voltage applied between the source and the substrate, and
VFB, and S are parameters that depend on the process technology.

If Vdd is the power supply voltage, i.e., the maximum voltage that can be applied between the gate and source, the on current can be written as

(3)

The active power can then be expressed as

(4)

Leakage power:

There are four main components of leakage in a MOS transistor.
1. Junction leakage: The p-n junction between the drain and substrate or source and substrate is negatively biased when the transistor is off. This results in a leakage current due to the presence of the reverse bias diode.
2. Gate leakage: The presence of a high electric field in gate oxide cases electrons to tunnel through the gate into the substrate resulting in gate leakage. As transistor geometries shrink the gate oxide thickness is reduced making it more prone to tunneling. However, new hi-k dielectric materials for the gate oxide have managed to control this leakage and keep it to a minimum.
3. Gate induced drain leakage: The high electric fields in the gate-drain overlap region cause band-to-band tunneling resulting in gate-induced drain leakage current.
4. Subthreshold conduction: When the transistor is off, it is not truly turned off, but conducts due to weak inversion. This is called subthreshold conduction and is the main contributor of leakage current. This current can be expressed as

(5)

Where k1, , , and n are technology dependent, T is the thermal voltage, and k1 is a function of the gate oxide thickness.

The off current or leakage current in a transistor can be obtained by setting Vgs = 0 and Vds = Vdd.

Under these conditions, the term 1Cexp(CVdd/T can be approximated to 1 since Vdd >>T Leading to

(6)

The leakage power can now be written as

(7)


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